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<instructionsection id="CBNZ_a32" title="CBNZ, CBZ -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="T32"/>
  </docvars>
  <heading>CBNZ, CBZ</heading>
  <desc>
    <brief>
      <para>Compare and Branch on Nonzero or Zero</para>
    </brief>
    <authored>
      <para>Compare and Branch on Nonzero and Compare and Branch on Zero
compare the value in a register with zero, and conditionally branch
forward a constant value. They do not affect the condition flags.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> behavior, see <xref linkend="ARMARM_CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="16" psname="T32.n.misc16.cbznz16.CBNZ_T1">
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="1" name="op" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="10" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="1" name="i" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="8" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="5" name="imm5" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="2" width="3" name="Rn" usename="1">
          <c colspan="3"/>
        </box>
      </regdiagram>
      <encoding name="CBNZ_T1" oneofinclass="2" oneof="2" label="CBNZ" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="CBNZ"/>
        </docvars>
        <box hibit="11" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>CBNZ{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qn_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose register to be tested, encoded in the &quot;Rn&quot; field." link="Rn__40">&lt;Rn&gt;</a><text>, </text><a hover="Is the program label to be conditionally branched to. Its offset from the PC, a multiple of 2 and in the range 0 to 126, is encoded as &quot;i:imm5&quot; times 2." link="i_imm5">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CBZ_T1" oneofinclass="2" oneof="2" label="CBZ" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="CBZ"/>
        </docvars>
        <box hibit="11" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>CBZ{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qn_option">&lt;q&gt;</a><text>}  </text><a hover="Is the general-purpose register to be tested, encoded in the &quot;Rn&quot; field." link="Rn__40">&lt;Rn&gt;</a><text>, </text><a hover="Is the program label to be conditionally branched to. Its offset from the PC, a multiple of 2 and in the range 0 to 126, is encoded as &quot;i:imm5&quot; times 2." link="i_imm5">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.n.misc16.cbznz16.CBNZ_T1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(i::imm5::'0');
let nonzero : boolean = (op == '1');
if InITBlock() then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CBNZ_T1, CBZ_T1" symboldefcount="1">
      <symbol link="qn_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CBNZ_T1, CBZ_T1" symboldefcount="1">
      <symbol link="Rn__40">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose register to be tested, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CBNZ_T1, CBZ_T1" symboldefcount="1">
      <symbol link="i_imm5">&lt;label&gt;</symbol>
      <account encodedin="(i :: imm5)">
        <intro>
          <para>Is the program label to be conditionally branched to. Its offset from the PC, a multiple of 2 and in the range 0 to 126, is encoded as "i:imm5" times 2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="T32.n.misc16.cbznz16.CBNZ_T1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">EncodingSpecificOperations();
if nonzero != IsZero(R(n)) then
    CBWritePC(PC32() + imm32);
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
