<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2025 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="DCPS2_a32" title="DCPS2 -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="T32"/>
    <docvar key="mnemonic" value="DCPS2"/>
  </docvars>
  <heading>DCPS2</heading>
  <desc>
    <brief>
      <para>Debug Change PE State to EL2</para>
    </brief>
    <authored>
      <para>Debug Change PE State to EL2 allows the debugger to move the PE into
EL2 from a lower Exception level.</para>
      <para><instruction>DCPS2</instruction> is <arm-defined-word>UNDEFINED</arm-defined-word> if any of:</para>
      <list type="unordered">
        <listitem>
          <content>The PE is in Non-debug state.</content>
        </listitem>
        <listitem>
          <content>EL2 is not implemented.</content>
        </listitem>
        <listitem>
          <content>The PE is in Secure state and any of:<list type="unordered">
              <listitem>
                <content>Secure EL2 is not implemented.</content>
              </listitem>
              <listitem>
                <content>Secure EL2 is implemented and Secure EL2 is disabled.</content>
              </listitem>
            </list>
          </content>
        </listitem>
      </list>
      <para>When the PE executes <instruction>DCPS2</instruction>:</para>
      <list type="unordered">
        <listitem>
          <content>If EL2 is using AArch32, the PE enters Hyp mode and ELR_hyp, HSR, SPSR_hyp, DLR and DSPSR become <arm-defined-word>UNKNOWN</arm-defined-word>.</content>
        </listitem>
        <listitem>
          <content>If EL2 is using AArch64, the PE enters EL2 using AArch64, selects SP_EL2, and ELR_EL2, ESR_EL2, SPSR_EL2, DLR_EL0 and DSPSR_EL0 become <arm-defined-word>UNKNOWN</arm-defined-word>.</content>
        </listitem>
      </list>
      <para>For more information on the operation of the DCPS&lt;n&gt; instructions, see <xref linkend="ARMARM_dcps">DCPS</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="DCPS2"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="16x2" psname="T32.w.bcrtrl.dcps.DCPS2_T1" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="25" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1" settings="4" psbits="xxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="10" name="imm10" usename="1" settings="10" psbits="xxxxxxxxxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="1" width="2" name="opt" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="DCPS2_T1" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="DCPS2"/>
        </docvars>
        <asmtemplate><text>DCPS2</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.bcrtrl.dcps.DCPS2_T1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !HaveEL(EL2) then Undefined(); end;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all"/>
  <ps_section howmany="1">
    <ps name="T32.w.bcrtrl.dcps.DCPS2_T1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if !Halted() || !EL2Enabled() then Undefined(); end;

if ELUsingAArch32(EL2) then
    AArch32_WriteMode(M32_Hyp);
    PSTATE.E = HSCTLR().EE;

    ELR_hyp() = ARBITRARY : bits(32);
    HSR() = ARBITRARY : bits(32);
    SPSR_hyp() = ARBITRARY : bits(32);

    DLR() = ARBITRARY : bits(32);
    DSPSR() = ARBITRARY : bits(32);
else                                        // Targeting EL2 using AArch64
    AArch64_MaybeZeroRegisterUppers();
    MaybeZeroSVEUppers(EL2);
    PSTATE.nRW = '0';
    PSTATE.SP = '1';
    PSTATE.EL = EL2;
    if IsFeatureImplemented(FEAT_PAN) &amp;&amp; SCTLR_EL2().SPAN == '0' &amp;&amp; ELIsInHost(EL0) then
        PSTATE.PAN = '1';
    end;
    if IsFeatureImplemented(FEAT_UAO) then PSTATE.UAO = '0'; end;

    ELR_EL2() = ARBITRARY : bits(64);
    ESR_EL2() = ARBITRARY : bits(64);
    SPSR_EL2() = ARBITRARY : bits(64);

    DLR_EL0() = ARBITRARY : bits(64);
    DSPSR_EL0() = ARBITRARY : bits(64);

    // SCTLR_EL2.IESB might be ignored in Debug state.
    if (IsFeatureImplemented(FEAT_IESB) &amp;&amp; SCTLR_EL2().IESB == '1' &amp;&amp;
          !ConstrainUnpredictableBool(Unpredictable_IESBinDebug)) then
        SynchronizeErrors();
    end;
end;

UpdateEDSCRFields();                        // Update EDSCR PE state flags</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
