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<instructionsection id="DCPS3_a32" title="DCPS3 -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="T32"/>
    <docvar key="mnemonic" value="DCPS3"/>
  </docvars>
  <heading>DCPS3</heading>
  <desc>
    <brief>
      <para>Debug Change PE State to EL3</para>
    </brief>
    <authored>
      <para>Debug Change PE State to EL3 allows the debugger to move the PE into
EL3 from a lower Exception level or to a specific mode at the
current Exception level.</para>
      <para><instruction>DCPS3</instruction> is <arm-defined-word>UNDEFINED</arm-defined-word> if any of:</para>
      <list type="unordered">
        <listitem>
          <content>The PE is in Non-debug state.</content>
        </listitem>
        <listitem>
          <content>EL3 is not implemented.</content>
        </listitem>
        <listitem>
          <content>EDSCR.SDD is set to 1.</content>
        </listitem>
      </list>
      <para>When the PE executes <instruction>DCPS3</instruction>:</para>
      <list type="unordered">
        <listitem>
          <content>If EL3 is using AArch32, the PE enters Monitor mode and LR_mon, SPSR_mon, DLR and DSPSR become <arm-defined-word>UNKNOWN</arm-defined-word>. If <instruction>DCPS3</instruction> is executed in Monitor mode, SCR.NS is cleared to 0.</content>
        </listitem>
        <listitem>
          <content>If EL3 is using AArch64, the PE enters EL3 using AArch64, selects SP_EL3, and ELR_EL3, ESR_EL3, SPSR_EL3, DLR_EL0 and DSPSR_EL0 become <arm-defined-word>UNKNOWN</arm-defined-word>.</content>
        </listitem>
      </list>
      <para>For more information on the operation of the DCPS&lt;n&gt; instructions, see <xref linkend="ARMARM_dcps">DCPS</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="DCPS3"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="16x2" psname="T32.w.bcrtrl.dcps.DCPS3_T1" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="25" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1" settings="4" psbits="xxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="10" name="imm10" usename="1" settings="10" psbits="xxxxxxxxxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="1" width="2" name="opt" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="DCPS3_T1" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="DCPS3"/>
        </docvars>
        <asmtemplate><text>DCPS3</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.bcrtrl.dcps.DCPS3_T1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !HaveEL(EL3) then Undefined(); end;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all"/>
  <ps_section howmany="1">
    <ps name="T32.w.bcrtrl.dcps.DCPS3_T1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if !Halted() || EDSCR().SDD == '1' then Undefined(); end;

if ELUsingAArch32(EL3) then
    let from_secure : boolean = (CurrentSecurityState() == SS_Secure);
    if PSTATE.M == M32_Monitor then SCR().NS = '0'; end;
    AArch32_WriteMode(M32_Monitor);
    if IsFeatureImplemented(FEAT_PAN) then
        if !from_secure then
            PSTATE.PAN = '0';
        elsif SCTLR().SPAN == '0' then
            PSTATE.PAN = '1';
        end;
    end;
    PSTATE.E = SCTLR().EE;

    LR_mon = ARBITRARY : bits(32);
    SPSR_mon() = ARBITRARY : bits(32);

    DLR() = ARBITRARY : bits(32);
    DSPSR() = ARBITRARY : bits(32);
else                                        // Targeting EL3 using AArch64
    AArch64_MaybeZeroRegisterUppers();
    MaybeZeroSVEUppers(EL3);
    PSTATE.nRW = '0';
    PSTATE.SP = '1';
    PSTATE.EL = EL3;
    if IsFeatureImplemented(FEAT_UAO) then PSTATE.UAO = '0'; end;

    ELR_EL3() = ARBITRARY : bits(64);
    ESR_EL3() = ARBITRARY : bits(64);
    SPSR_EL3() = ARBITRARY : bits(64);

    DLR_EL0() = ARBITRARY : bits(64);
    DSPSR_EL0() = ARBITRARY : bits(64);

    var sync_errors : boolean = IsFeatureImplemented(FEAT_IESB) &amp;&amp; SCTLR_EL3().IESB == '1';
    if IsFeatureImplemented(FEAT_DoubleFault) &amp;&amp; EffectiveEA() == '1' &amp;&amp; SCR_EL3().NMEA == '1' then
        sync_errors = TRUE;
    end;
    // SCTLR_EL3.IESB might be ignored in Debug state.
    if !ConstrainUnpredictableBool(Unpredictable_IESBinDebug) then
        sync_errors = FALSE;
    end;
    if sync_errors then SynchronizeErrors(); end;
end;

UpdateEDSCRFields();                        // Update EDSCR PE state flags</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
