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<instructionsection id="DMB_a32" title="DMB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="mnemonic" value="DMB"/>
  </docvars>
  <heading>DMB</heading>
  <desc>
    <brief>
      <para>Data Memory Barrier</para>
    </brief>
    <authored>
      <para>Data Memory Barrier is a memory barrier that ensures the ordering of
observations of memory accesses, see <xref linkend="ARMARM_AA32CHDCIFHJ">Data
Memory Barrier (DMB)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> behavior, see <xref linkend="ARMARM_CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A32"/>
        <docvar key="mnemonic" value="DMB"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A32.uncond_as.uncondhints.barriers.DMB_A1" tworows="1">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="27" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="25" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="12" settings="12">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" name="opcode" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="DMB_A1" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="DMB"/>
        </docvars>
        <asmtemplate><text>DMB{</text><a hover="For the &quot;A1&quot; variant: see x[Standard assembler syntax fields](Babbefhf). Must be AL or omitted." link="AL_option__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  {</text><a hover="Specifies an optional limitation on the barrier operation. Values are:&#10;&#10;&#10;SY&#10;: Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Can be omitted. This option is referred to as the full system barrier. Encoded as option = 0b1111.&#10;&#10;ST&#10;: Full system is the required shareability domain, writes are the required access type, both before and after the barrier instruction. SYST is a synonym for ST. Encoded as option = 0b1110.&#10;&#10;LD&#10;: Full system is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b1101.&#10;&#10;ISH&#10;: Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = 0b1011.&#10;&#10;ISHST&#10;: Inner Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = 0b1010.&#10;&#10;ISHLD&#10;: Inner Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b1001.&#10;&#10;NSH&#10;: Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as option = 0b0111.&#10;&#10;NSHST&#10;: Non-shareable is the required shareability domain, writes are the required access type both before and after the barrier instruction. Encoded as option = 0b0110.&#10;&#10;NSHLD&#10;: Non-shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b0101.&#10;&#10;OSH&#10;: Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = 0b0011.&#10;&#10;OSHST&#10;: Outer Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = 0b0010.&#10;&#10;OSHLD&#10;: Outer Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b0001.&#10;&#10;&#10;&#10;For more information on whether an access is before or after a barrier instruction, see x[Data Memory Barrier (DMB)](AA32CHDCIFHJ). All other encodings of option are reserved. All unsupported and reserved options must execute as a full system DMB operation, but software must not rely on this behavior.&#10;&#10;&#10;[note]&#10;The instruction supports the following alternative &lt;option&gt; values, but Arm recommends that software does not use these alternative values:&#10;&#10;  * SH as an alias for ISH.&#10;  * SHST as an alias for ISHST.&#10;  * UN as an alias for NSH.&#10;  * UNST as an alias for NSHST.&#10;[/note]" link="CRm_option__5">&lt;option&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A32.uncond_as.uncondhints.barriers.DMB_A1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">// No additional decoding required</pstext></ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="DMB"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="16x2" psname="T32.w.bcrtrl.system.DMB_T1" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="15" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" width="3" settings="3">
          <c>0</c>
          <c>(0)</c>
          <c>0</c>
        </box>
        <box hibit="11" width="1" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" name="opc" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="DMB_T1" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="DMB"/>
        </docvars>
        <asmtemplate><text>DMB{</text><a hover="For the &quot;T1&quot; variant: see x[Standard assembler syntax fields](Babbefhf)." link="AL_option__6">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  {</text><a hover="Specifies an optional limitation on the barrier operation. Values are:&#10;&#10;&#10;SY&#10;: Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Can be omitted. This option is referred to as the full system barrier. Encoded as option = 0b1111.&#10;&#10;ST&#10;: Full system is the required shareability domain, writes are the required access type, both before and after the barrier instruction. SYST is a synonym for ST. Encoded as option = 0b1110.&#10;&#10;LD&#10;: Full system is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b1101.&#10;&#10;ISH&#10;: Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = 0b1011.&#10;&#10;ISHST&#10;: Inner Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = 0b1010.&#10;&#10;ISHLD&#10;: Inner Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b1001.&#10;&#10;NSH&#10;: Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as option = 0b0111.&#10;&#10;NSHST&#10;: Non-shareable is the required shareability domain, writes are the required access type both before and after the barrier instruction. Encoded as option = 0b0110.&#10;&#10;NSHLD&#10;: Non-shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b0101.&#10;&#10;OSH&#10;: Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = 0b0011.&#10;&#10;OSHST&#10;: Outer Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = 0b0010.&#10;&#10;OSHLD&#10;: Outer Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b0001.&#10;&#10;&#10;&#10;For more information on whether an access is before or after a barrier instruction, see x[Data Memory Barrier (DMB)](AA32CHDCIFHJ). All other encodings of option are reserved. All unsupported and reserved options must execute as a full system DMB operation, but software must not rely on this behavior.&#10;&#10;&#10;[note]&#10;The instruction supports the following alternative &lt;option&gt; values, but Arm recommends that software does not use these alternative values:&#10;&#10;  * SH as an alias for ISH.&#10;  * SHST as an alias for ISHST.&#10;  * UN as an alias for NSH.&#10;  * UNST as an alias for NSHST.&#10;[/note]" link="CRm_option__5">&lt;option&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.bcrtrl.system.DMB_T1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">// No additional decoding required</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="DMB_A1" symboldefcount="1">
      <symbol link="AL_option__2">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For the "A1" variant: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DMB_T1" symboldefcount="2">
      <symbol link="AL_option__6">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For the "T1" variant: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DMB_A1, DMB_T1" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DMB_A1, DMB_T1" symboldefcount="1">
      <symbol link="CRm_option__5">&lt;option&gt;</symbol>
      <account encodedin="option">
        <intro>
          <para>Specifies an optional limitation on the barrier operation. Values are:</para>
          <list type="param">
            <listitem>
              <param>SY</param>
              <content>Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Can be omitted. This option is referred to as the full system barrier. Encoded as option = <binarynumber>0b1111</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ST</param>
              <content>Full system is the required shareability domain, writes are the required access type, both before and after the barrier instruction. <value>SYST</value> is a synonym for <value>ST</value>. Encoded as option = <binarynumber>0b1110</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>LD</param>
              <content>Full system is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b1101</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISH</param>
              <content>Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = <binarynumber>0b1011</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISHST</param>
              <content>Inner Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = <binarynumber>0b1010</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISHLD</param>
              <content>Inner Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b1001</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSH</param>
              <content>Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as option = <binarynumber>0b0111</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSHST</param>
              <content>Non-shareable is the required shareability domain, writes are the required access type both before and after the barrier instruction. Encoded as option = <binarynumber>0b0110</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSHLD</param>
              <content>Non-shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b0101</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSH</param>
              <content>Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = <binarynumber>0b0011</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSHST</param>
              <content>Outer Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = <binarynumber>0b0010</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSHLD</param>
              <content>Outer Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b0001</binarynumber>.</content>
            </listitem>
          </list>
          <para>For more information on whether an access is before or after a barrier instruction, see <xref linkend="AA32CHDCIFHJ">Data Memory Barrier (DMB)</xref>. All other encodings of option are reserved. All unsupported and reserved options must execute as a full system DMB operation, but software must not rely on this behavior.</para>
          <note>
            <para>The instruction supports the following alternative <syntax>&lt;option&gt;</syntax> values, but Arm recommends that software does not use these alternative values:</para>
            <list type="unordered">
              <listitem>
                <content>
                  <value>SH</value> as an alias for <value>ISH</value>.</content>
              </listitem>
              <listitem>
                <content>
                  <value>SHST</value> as an alias for <value>ISHST</value>.</content>
              </listitem>
              <listitem>
                <content>
                  <value>UN</value> as an alias for <value>NSH</value>.</content>
              </listitem>
              <listitem>
                <content>
                  <value>UNST</value> as an alias for <value>NSHST</value>.</content>
              </listitem>
            </list>
          </note>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A32.uncond_as.uncondhints.barriers.DMB_A1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if ConditionPassed() then
    EncodingSpecificOperations();
    var domain : MBReqDomain;
    var types : <a link="MBReqTypes" file="shared_pseudocode.xml" hover="type MBReqTypes">MBReqTypes</a>;
    case option of
        when '0001' =&gt;  domain = MBReqDomain_OuterShareable;  types = MBReqTypes_Reads;
        when '0010' =&gt;  domain = MBReqDomain_OuterShareable;  types = MBReqTypes_Writes;
        when '0011' =&gt;  domain = MBReqDomain_OuterShareable;  types = MBReqTypes_All;
        when '0101' =&gt;  domain = MBReqDomain_Nonshareable;    types = MBReqTypes_Reads;
        when '0110' =&gt;  domain = MBReqDomain_Nonshareable;    types = MBReqTypes_Writes;
        when '0111' =&gt;  domain = MBReqDomain_Nonshareable;    types = MBReqTypes_All;
        when '1001' =&gt;  domain = MBReqDomain_InnerShareable;  types = MBReqTypes_Reads;
        when '1010' =&gt;  domain = MBReqDomain_InnerShareable;  types = MBReqTypes_Writes;
        when '1011' =&gt;  domain = MBReqDomain_InnerShareable;  types = MBReqTypes_All;
        when '1101' =&gt;  domain = MBReqDomain_FullSystem;      types = MBReqTypes_Reads;
        when '1110' =&gt;  domain = MBReqDomain_FullSystem;      types = MBReqTypes_Writes;
        otherwise =&gt;    domain = MBReqDomain_FullSystem;      types = MBReqTypes_All;
    end;

    if PSTATE.EL IN {EL0, EL1} &amp;&amp; EL2Enabled() then
        if HCR().BSU == '11' then
            domain = MBReqDomain_FullSystem;
        end;
        if HCR().BSU == '10' &amp;&amp; domain != MBReqDomain_FullSystem then
            domain = MBReqDomain_OuterShareable;
        end;
        if HCR().BSU == '01' &amp;&amp; domain == MBReqDomain_Nonshareable then
            domain = MBReqDomain_InnerShareable;
        end;
    end;

    DataMemoryBarrier(domain, types);
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
