LDAEXD
Load-Acquire Exclusive Doubleword
Load-Acquire Exclusive Doubleword loads a doubleword from memory,
writes it to two registers and:
If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor
Causes the executing PE to indicate an active exclusive access in the local monitor.
The instruction also acts as a barrier instruction with the ordering
requirements described in Load-Acquire,
Store-Release.
For more information about support for shared memory see
Synchronization and semaphores. For
information about memory accesses see Memory
accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
0
0
0
1
1
0
1
1
(1)
(1)
1
0
1
0
0
1
(1)
(1)
(1)
(1)
LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]
let t : integer = UInt(Rt);
let t2 : integer = t + 1;
let n : integer = UInt(Rn);
if Rt[0] == '1' || t2 == 15 || n == 15 then UnpredictableProcedure(); end;
Rt<0> == '1'
Rt == '1110'
The instruction is handled as described in Using R15.
1
1
1
0
1
0
0
0
1
1
0
1
1
1
1
1
(1)
(1)
(1)
(1)
LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]
let t : integer = UInt(Rt);
let t2 : integer = UInt(Rt2);
let n : integer = UInt(Rn);
if t == 15 || t2 == 15 || t == t2 || n == 15 then UnpredictableProcedure(); end;
t == t2
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
For the "A1" variant: is the first general-purpose register to be transferred, encoded in the "Rt" field. <Rt> must be even-numbered and not R14.
<Rt>
For the "T1" variant: is the first general-purpose register to be transferred, encoded in the "Rt" field.
<Rt2>
For the "A1" variant: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>.
<Rt2>
For the "T1" variant: is the second general-purpose register to be transferred, encoded in the "Rt2" field.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field.
if ConditionPassed() then
EncodingSpecificOperations();
let address : bits(32) = R(n);
AArch32_SetExclusiveMonitors(address, 8);
let value : bits(64) = MemO{64}(address);
// Extract words from 64-bit loaded value such that R[t] is
// loaded from address and R[t2] from address+4.
R(t) = if BigEndian(AccessType_GPR) then value[63:32] else value[31:0];
R(t2) = if BigEndian(AccessType_GPR) then value[31:0] else value[63:32];
end;
2026-03-12 12:23:09
2025-09_rel_asl1