LDR (literal)
Load Register (literal)
Load Register (literal) calculates an address from the PC value and
an immediate offset, loads a word from memory, and writes it to a
register. For information about memory accesses see
Memory accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
1
0
0
1
1
1
1
1
LDR{<c>}{<q>} <Rt>, <label>
LDR{<c>}{<q>} <Rt>, [PC, #{+/-}<imm>]
if P == '0' && W == '1' then See("LDRT"); end;
let t : integer = UInt(Rt);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let add : boolean = (U == '1');
let wback : boolean = (P == '0') || (W == '1');
if wback then UnpredictableProcedure(); end;
wback
The instruction treats bit[24] as the P bit, and bit[21] as the writeback (W) bit, and uses the same addressing mode as described in LDR (immediate). The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in Using R15.
0
1
0
0
1
LDR{<c>}{<q>} <Rt>, <label>
let t : integer = UInt(Rt);
let imm32 : bits(32) = ZeroExtend{}(imm8::'00');
let add : boolean = TRUE;
1
1
1
1
1
0
0
0
1
0
1
1
1
1
1
LDR{<c>}.W <Rt>, <label>
LDR{<c>}{<q>} <Rt>, <label>
LDR{<c>}{<q>} <Rt>, [PC, #{+/-}<imm>]
let t : integer = UInt(Rt);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let add : boolean = (U == '1');
if t == 15 && InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
For the "A1" variant: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
<Rt>
For the "T1" variant: is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rt>
For the "T2" variant: is the general-purpose register to be transferred, encoded in the "Rt" field. The SP can be used. The PC can be used, provided the instruction is either outside an IT block or the last instruction of an IT block. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
<label>
For the "A1" and "T2" variants: the label of the literal data item that is to be loaded into <Rt>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Permitted values of the offset are -4095 to 4095.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE, encoded as U == 1.
If the offset is negative, imm32 is equal to minus the offset and add == FALSE, encoded as U == 0.
<label>
For the "T1" variant: the label of the literal data item that is to be loaded into <Rt>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Permitted values of the offset are Multiples of four in the range 0 to 1020.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For the "A1" variant: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.
<imm>
For the "T2" variant: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.
if ConditionPassed() then
EncodingSpecificOperations();
let base : bits(32) = AlignDownSize(PC32(),4);
let address : bits(32) = if add then (base + imm32) else (base - imm32);
let data : bits(32) = MemU{32}(address);
if t == 15 then
if address[1:0] == '00' then
LoadWritePC(data);
else
UnpredictableProcedure();
end;
else
R(t) = data;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1