LDR (register)
Load Register (register)
Load Register (register) calculates an address from a base register
value and an offset register value, loads a word from memory, and
writes it to a register. The offset register value can optionally be
shifted. For information about memory accesses, see
Memory accesses.
The T32 form of LDR (register) does not support register
writeback.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
1
1
0
1
0
1
0
LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]
0
0
LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>}
1
1
LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]!
if P == '0' && W == '1' then See("LDRT"); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (P == '0') || (W == '1');
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm5);
if m == 15 then UnpredictableProcedure(); end;
if wback && (n == 15 || n == t) then UnpredictableProcedure(); end;
wback && n == t
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.
0
1
0
1
1
0
0
LDR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>]
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let shift_t : SRType = SRType_LSL;
let shift_n : integer = 0;
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
1
1
1
1
1
0
0
0
0
1
0
1
!= 1111
0
0
0
0
0
0
LDR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>{, LSL #<imm>}]
LDR{<c>}.W <Rt>, [<Rn>, {+}<Rm>]
if Rn == '1111' then See("LDR (literal)"); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let shift_t : SRType = SRType_LSL;
let shift_n : integer = UInt(imm2);
// Armv8-A removes UNPREDICTABLE for R13
if m == 15 then UnpredictableProcedure(); end;
if t == 15 && InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
For the "A1 Offset", "A1 Post-indexed", and "A1 Pre-indexed" variants: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used. If the PC is used, the instruction branches to the address (data) loaded to the PC. This branch is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
<Rt>
For the "T1" variant: is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rt>
For the "T2" variant: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, provided the instruction is either outside an IT block or the last instruction of an IT block. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
<Rn>
For the "A1 Offset", "A1 Post-indexed", and "A1 Pre-indexed" variants: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.
<Rn>
For the "T1" and "T2" variants: is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
<Rm>
Is the general-purpose index register, encoded in the "Rm" field.
<shift>
The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts applied to a register.
+
Specifies the index register is added to the base register.
<imm>
If present, the size of the left shift to apply to the value from <Rm>, in the range 1-3. <imm> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as 0b00.
if CurrentInstrSet() == InstrSet_A32 then
if ConditionPassed() then
EncodingSpecificOperations();
let offset : bits(32) = Shift{}(R(m), shift_t, shift_n, PSTATE.C);
let offset_addr : bits(32) = if add then (R(n) + offset) else (R(n) - offset);
let address : bits(32) = if index then offset_addr else R(n);
let data : bits(32) = MemU{32}(address);
if wback then R(n) = offset_addr; end;
if t == 15 then
if address[1:0] == '00' then
LoadWritePC(data);
else
UnpredictableProcedure();
end;
else
R(t) = data;
end;
end;
else
if ConditionPassed() then
EncodingSpecificOperations();
let offset : bits(32) = Shift{}(R(m), shift_t, shift_n, PSTATE.C);
let offset_addr : bits(32) = (R(n) + offset);
let address : bits(32) = offset_addr;
let data : bits(32) = MemU{32}(address);
if t == 15 then
if address[1:0] == '00' then
LoadWritePC(data);
else
UnpredictableProcedure();
end;
else
R(t) = data;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1