LDRB (immediate)
Load Register Byte (immediate)
Load Register Byte (immediate) calculates an address from a base
register value and an immediate offset, loads a byte from memory,
zero-extends it to form a 32-bit word, and writes it to a
register. It can use offset, post-indexed, or pre-indexed
addressing. For information about memory accesses see
Memory accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
,
T2
and
T3
)
.
!= 1111
0
1
0
1
1
!= 1111
1
0
LDRB{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}]
0
0
LDRB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
LDRB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if Rn == '1111' then See("LDRB (literal)"); end;
if P == '0' && W == '1' then See("LDRBT"); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (P == '0') || (W == '1');
if t == 15 || (wback && n == t) then UnpredictableProcedure(); end;
wback && n == t
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.
0
1
1
1
1
LDRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm5);
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
1
1
1
1
1
0
0
0
1
0
0
1
!= 1111
!= 1111
LDRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
LDRB{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}]
if Rt == '1111' then See("PLD"); end;
if Rn == '1111' then See("LDRB (literal)"); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let index : boolean = TRUE;
let add : boolean = TRUE;
let wback : boolean = FALSE;
// Armv8-A removes UNPREDICTABLE for R13
1
1
1
1
1
0
0
0
0
0
0
1
!= 1111
1
N
N
N
N
1
0
0
LDRB{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}]
0
1
LDRB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>
1
1
LDRB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!
if Rt == '1111' && P == '1' && U == '0' && W == '0' then See("PLD, PLDW (immediate)"); end;
if Rn == '1111' then See("LDRB (literal)"); end;
if P == '1' && U == '1' && W == '0' then See("LDRBT"); end;
if P == '0' && W == '0' then Undefined(); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm8);
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (W == '1');
if (t == 15 && W == '1') || (wback && n == t) then UnpredictableProcedure(); end;
// Armv8-A removes UNPREDICTABLE for R13
wback && n == t
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>
For the "A1 Offset", "A1 Post-indexed", "A1 Pre-indexed", "T2", "T3 Offset", "T3 Post-indexed", and "T3 Pre-indexed" variants: is the general-purpose base register, encoded in the "Rn" field. For PC use see LDRB (literal).
<Rn>
For the "T1" variant: is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For the "A1 Offset", "A1 Post-indexed", and "A1 Pre-indexed" variants: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.
<imm>
For the "T1" variant: is an optional 5-bit unsigned immediate byte offset, in the range 0 to 31, defaulting to 0 and encoded in the "imm5" field.
<imm>
For the "T2" variant: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<imm>
For the "T3 Offset", "T3 Post-indexed", and "T3 Pre-indexed" variants: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.
+
Specifies the offset is added to the base register.
if CurrentInstrSet() == InstrSet_A32 then
if ConditionPassed() then
EncodingSpecificOperations();
let offset_addr : bits(32) = if add then (R(n) + imm32) else (R(n) - imm32);
let address : bits(32) = if index then offset_addr else R(n);
R(t) = ZeroExtend{32}(MemU{8}(address));
if wback then R(n) = offset_addr; end;
end;
else
if ConditionPassed() then
EncodingSpecificOperations();
let offset_addr : bits(32) = if add then (R(n) + imm32) else (R(n) - imm32);
let address : bits(32) = if index then offset_addr else R(n);
R(t) = ZeroExtend{32}(MemU{8}(address));
if wback then R(n) = offset_addr; end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1