LDRD (immediate)
Load Register Dual (immediate)
Load Register Dual (immediate) calculates an address from a base
register value and an immediate offset, loads two words from memory,
and writes them to two registers. It can use offset, post-indexed,
or pre-indexed addressing. For information about memory accesses see
Memory accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related encodings: Load/store dual, load/store exclusive, table branch.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
0
0
0
1
0
!= 1111
1
1
0
1
1
0
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}]
0
0
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm>
1
1
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]!
if Rn == '1111' then See("LDRD (literal)"); end;
if Rt[0] == '1' then UnpredictableProcedure(); end;
let t : integer = UInt(Rt);
let t2 : integer = t + 1;
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm4H::imm4L);
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (P == '0') || (W == '1');
if P == '0' && W == '1' then UnpredictableProcedure(); end;
if wback && (n == t || n == t2) then UnpredictableProcedure(); end;
if t2 == 15 then UnpredictableProcedure(); end;
wback && (n == t || n == t2)
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.
P == '0' && W == '1'
The instruction executes as an LDRD using one of offset, post-indexed, or pre-indexed addressing.
Rt<0> == '1'
The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.
1
1
1
0
1
0
0
1
1
!= 1111
1
0
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}]
0
1
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm>
1
1
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]!
if P == '0' && W == '0' then See("Related encodings"); end;
if Rn == '1111' then See("LDRD (literal)"); end;
let t : integer = UInt(Rt);
let t2 : integer = UInt(Rt2);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm8::'00');
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (W == '1');
if wback && (n == t || n == t2) then UnpredictableProcedure(); end;
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 || t2 == 15 || t == t2 then UnpredictableProcedure(); end;
wback && (n == t || n == t2)
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.
t == t2
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
For the "A1 Offset", "A1 Post-indexed", and "A1 Pre-indexed" variants: is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.
<Rt>
For the "T1 Offset", "T1 Post-indexed", and "T1 Pre-indexed" variants: is the first general-purpose register to be transferred, encoded in the "Rt" field.
<Rt2>
For the "A1 Offset", "A1 Post-indexed", and "A1 Pre-indexed" variants: is the second general-purpose register to be transferred. This register must be <R(t+1)>.
<Rt2>
For the "T1 Offset", "T1 Post-indexed", and "T1 Pre-indexed" variants: is the second general-purpose register to be transferred, encoded in the "Rt2" field.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field. For PC use see LDRD (literal).
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For the "A1 Offset", "A1 Post-indexed", and "A1 Pre-indexed" variants: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.
<imm>
For the "T1 Offset", "T1 Post-indexed", and "T1 Pre-indexed" variants: is the unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0 if omitted, and encoded in the "imm8" field as <imm>/4.
if ConditionPassed() then
EncodingSpecificOperations();
let offset_addr : bits(32) = if add then (R(n) + imm32) else (R(n) - imm32);
let address : bits(32) = if index then offset_addr else R(n);
if IsAlignedSize(address, 8) then
let data : bits(64) = MemA{64}(address);
if BigEndian(AccessType_GPR) then
R(t) = data[63:32];
R(t2) = data[31:0];
else
R(t) = data[31:0];
R(t2) = data[63:32];
end;
else
let data1 : bits(32) = MemA{32}(address);
let data2 : bits(32) = MemA{32}(address+4);
R(t) = data1;
R(t2) = data2;
end;
if wback then R(n) = offset_addr; end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1