LDRD (register)
Load Register Dual (register)
Load Register Dual (register) calculates an address from a base
register value and a register offset, loads two words from memory,
and writes them to two registers. It can use offset, post-indexed,
or pre-indexed addressing. For information about memory accesses see
Memory accesses.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
!= 1111
0
0
0
0
0
(0)
(0)
(0)
(0)
1
1
0
1
1
0
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, {+/-}<Rm>]
0
0
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], {+/-}<Rm>
1
1
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, {+/-}<Rm>]!
if Rt[0] == '1' then UnpredictableProcedure(); end;
let t : integer = UInt(Rt);
let t2 : integer = t + 1;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let index : boolean = (P == '1');
let add : boolean = (U == '1');
let wback : boolean = (P == '0') || (W == '1');
if P == '0' && W == '1' then UnpredictableProcedure(); end;
if t2 == 15 || m == 15 || m == t || m == t2 then UnpredictableProcedure(); end;
if wback && (n == 15 || n == t || n == t2) then UnpredictableProcedure(); end;
wback && (n == t || n == t2)
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.
P == '0' && W == '1'
The instruction executes as an LDRD using one of offset, post-indexed, or pre-indexed addressing.
m == t || m == t2
The instruction loads register Rm with an UNKNOWN value.
Rt<0> == '1'
The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
Is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.
<Rt2>
Is the second general-purpose register to be transferred. This register must be <R(t+1)>.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.
+/-
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
<Rm>
Is the general-purpose index register, encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
let offset_addr : bits(32) = if add then (R(n) + R(m)) else (R(n) - R(m));
let address : bits(32) = if index then offset_addr else R(n);
if IsAlignedSize(address, 8) then
let data : bits(64) = MemA{64}(address);
if BigEndian(AccessType_GPR) then
R(t) = data[63:32];
R(t2) = data[31:0];
else
R(t) = data[31:0];
R(t2) = data[63:32];
end;
else
let data1 : bits(32) = MemA{32}(address);
let data2 : bits(32) = MemA{32}(address+4);
R(t) = data1;
R(t2) = data2;
end;
if wback then R(n) = offset_addr; end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1