LDREX Load Register Exclusive Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor. Causes the executing PE to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. This instruction is a data-independent-time instruction as described in About the DIT bit. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 1 0 0 1 (1) (1) 1 1 1 0 0 1 (1) (1) (1) (1) LDREX{<c>}{<q>} <Rt>, [<Rn> {, {#}<imm>}] let t : integer = UInt(Rt); let n : integer = UInt(Rn); let imm32 : bits(32) = Zeros{}; // Zero offset if t == 15 || n == 15 then UnpredictableProcedure(); end; 1 1 1 0 1 0 0 0 0 1 0 1 (1) (1) (1) (1) LDREX{<c>}{<q>} <Rt>, [<Rn> {, #<imm>}] let t : integer = UInt(Rt); let n : integer = UInt(Rn); let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || n == 15 then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rt> Is the general-purpose register to be transferred, encoded in the "Rt" field. <Rn> Is the general-purpose base register, encoded in the "Rn" field. <imm> For the "A1" variant: the immediate offset added to the value of <Rn> to calculate the address. <imm> can only be 0 or omitted. <imm> For the "T1" variant: the immediate offset added to the value of <Rn> to calculate the address. <imm> can be omitted, meaning an offset of 0. Values are multiples of 4 in the range 0-1020. if ConditionPassed() then EncodingSpecificOperations(); let address : bits(32) = R(n) + imm32; AArch32_SetExclusiveMonitors(address,4); R(t) = MemA{32}(address); end; 2026-03-12 12:23:09 2025-09_rel_asl1