MOV, MOVS (register-shifted register)
Move (register-shifted register)
Move (register-shifted register) copies a register-shifted register
value to the destination register. It can optionally update the
condition flags based on the value.
Related encodings: In encoding T1, for an op field value that is not described above, see Data-processing (two low registers).
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
This instruction is used by the aliases
ASRS (register)
S == '1' && stype == '10'
op == '0100' && !InITBlock()
stype == '10' && S == '1'
ASR (register)
S == '0' && stype == '10'
op == '0100' && InITBlock()
stype == '10' && S == '0'
LSLS (register)
S == '1' && stype == '00'
op == '0010' && !InITBlock()
stype == '00' && S == '1'
LSL (register)
S == '0' && stype == '00'
op == '0010' && InITBlock()
stype == '00' && S == '0'
LSRS (register)
S == '1' && stype == '01'
op == '0011' && !InITBlock()
stype == '01' && S == '1'
LSR (register)
S == '0' && stype == '01'
op == '0011' && InITBlock()
stype == '01' && S == '0'
RORS (register)
S == '1' && stype == '11'
op == '0111' && !InITBlock()
stype == '11' && S == '1'
ROR (register)
S == '0' && stype == '11'
op == '0111' && InITBlock()
stype == '11' && S == '0'
See
below for details of when each alias is preferred.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
0
0
1
1
0
1
(0)
(0)
(0)
(0)
0
1
1
MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs>
0
MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs>
let d : integer = UInt(Rd);
let m : integer = UInt(Rm);
let s : integer = UInt(Rs);
let setflags : boolean = (S == '1');
let shift_t : SRType = DecodeRegShift(stype);
if d == 15 || m == 15 || s == 15 then UnpredictableProcedure(); end;
0
1
0
0
0
0
0
x
x
x
1
0
0
MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs>
MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs>
0
1
0
MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs>
MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs>
0
1
1
MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs>
MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs>
1
1
1
MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs>
MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs>
if ! op IN {'0010', '0011', '0100', '0111'} then See("Related encodings"); end;
let d : integer = UInt(Rdm);
let m : integer = UInt(Rdm);
let s : integer = UInt(Rs);
let setflags : boolean = !InITBlock();
let shift_t : SRType = DecodeRegShift(op[2]::op[0]);
1
1
1
1
1
0
1
0
0
1
1
1
1
0
0
0
0
1
MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs>
MOVS.W <Rd>, <Rm>, <shift> <Rs>
0
MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs>
MOV<c>.W <Rd>, <Rm>, <shift> <Rs>
let d : integer = UInt(Rd);
let m : integer = UInt(Rm);
let s : integer = UInt(Rs);
let setflags : boolean = (S == '1');
let shift_t : SRType = DecodeRegShift(stype);
// Armv8-A removes UNPREDICTABLE for R13
if d == 15 || m == 15 || s == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rd>
Is the general-purpose destination register, encoded in the "Rd" field.
<Rm>
Is the general-purpose source register, encoded in the "Rm" field.
<shift>
Is the type of shift to be applied to the second source register,
stype
<shift>
00
LSL
01
LSR
10
ASR
11
ROR
<Rs>
Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.
<Rdm>
Is the general-purpose source register and the destination register, encoded in the "Rdm" field.
Alias Conditions
if ConditionPassed() then
EncodingSpecificOperations();
let shift_n : integer = UInt(R(s)[7:0]);
let (result, carry) : (bits(32), bit) = Shift_C{32}(R(m), shift_t, shift_n, PSTATE.C);
R(d) = result;
if setflags then
PSTATE.N = result[31];
PSTATE.Z = IsZeroBit{32}(result);
PSTATE.C = carry;
// PSTATE.V unchanged
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1