<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2025 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="MRRC" title="MRRC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="mnemonic" value="MRRC"/>
  </docvars>
  <heading>MRRC</heading>
  <desc>
    <brief>
      <para>Move to two general-purpose registers from System register</para>
    </brief>
    <authored>
      <para>Move to two general-purpose registers from System register.
This instruction copies the value of a System register to two
general-purpose registers.</para>
      <para>The System register descriptions identify valid encodings for this
instruction. Other encodings are <arm-defined-word>UNDEFINED</arm-defined-word>. For
more information see <xref linkend="ARMARM_CFIDGFBF">About the AArch32 System
register interface</xref> and <xref linkend="ARMARM_BABDFCJB">General behavior of
System registers</xref>.</para>
      <para>In an implementation that includes EL2, <instruction>MRRC</instruction> accesses to System
registers can be trapped to Hyp mode, meaning that an
attempt to execute an <instruction>MRRC</instruction> instruction in a Non-secure mode
other than Hyp mode, that would be permitted in the absence of the
Hyp trap controls, generates a Hyp Trap exception.  For more
information, see <xref linkend="ARMARM_BEIDFAFD">EL2 configurable instruction
enables, disables, and traps</xref>.</para>
      <para>Because of the range of possible traps to Hyp mode, the <instruction>MRRC</instruction>
pseudocode does not show these possible traps.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> behavior of this instruction, see <xref linkend="ARMARM_CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The possible values of { <syntax>&lt;coproc&gt;</syntax>, <syntax>&lt;opc1&gt;</syntax>, <syntax>&lt;CRm&gt;</syntax> } encode the entire System register encoding space. Not all of this space is allocated, and the System register descriptions identify the allocated encodings.</para>
      <para>For the permitted uses of these instructions, as described in this manual, <syntax>&lt;Rt2&gt;</syntax> transfers bits[63:32] of the selected System register, while <syntax>&lt;Rt&gt;</syntax> transfers bits[31:0].</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A32"/>
        <docvar key="mnemonic" value="MRRC"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A32.cops_as.sysldst_mov64.movcpgp64.MRRC_A1" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="cp15" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="7" width="4" name="opc1" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="MRRC_A1" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="MRRC"/>
        </docvars>
        <asmtemplate><text>MRRC{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the System register encoding space, " link="coproc_option">&lt;coproc&gt;</a><text>, {#}</text><a hover="Is the opc1 parameter within the System register encoding space, in the range 0 to 15, encoded in the &quot;opc1&quot; field." link="opc1__2">&lt;opc1&gt;</a><text>, </text><a hover="Is the first general-purpose register that is transferred into, encoded in the &quot;Rt&quot; field." link="Rt__18">&lt;Rt&gt;</a><text>, </text><a hover="Is the second general-purpose register that is transferred into, encoded in the &quot;Rt2&quot; field." link="Rt2__6">&lt;Rt2&gt;</a><text>, </text><a hover="Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the &quot;CRm&quot; field." link="CRm">&lt;CRm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A32.cops_as.sysldst_mov64.movcpgp64.MRRC_A1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let t : integer = UInt(Rt);
let t2 : integer = UInt(Rt2);
let cp : integer = if cp15 == '0' then 14 else 15;
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 || t2 == 15 || t == t2 then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">t == t2</pstext></cu_cause>
          <cu_type constraint="Constraint_UNDEF"/>
          <cu_type constraint="Constraint_NOP"/>
          <cu_type constraint="Constraint_UNKNOWN"/>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="MRRC"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="16x2" psname="T32.w.cpaf.sysldst_mov64.cp_mov64.MRRC_T1" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="cp15" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="7" width="4" name="opc1" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="MRRC_T1" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="MRRC"/>
        </docvars>
        <asmtemplate><text>MRRC{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  </text><a hover="Is the System register encoding space, " link="coproc_option">&lt;coproc&gt;</a><text>, {#}</text><a hover="Is the opc1 parameter within the System register encoding space, in the range 0 to 15, encoded in the &quot;opc1&quot; field." link="opc1__2">&lt;opc1&gt;</a><text>, </text><a hover="Is the first general-purpose register that is transferred into, encoded in the &quot;Rt&quot; field." link="Rt__18">&lt;Rt&gt;</a><text>, </text><a hover="Is the second general-purpose register that is transferred into, encoded in the &quot;Rt2&quot; field." link="Rt2__6">&lt;Rt2&gt;</a><text>, </text><a hover="Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the &quot;CRm&quot; field." link="CRm">&lt;CRm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.cpaf.sysldst_mov64.cp_mov64.MRRC_T1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let t : integer = UInt(Rt);
let t2 : integer = UInt(Rt2);
let cp : integer = if cp15 == '0' then 14 else 15;
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 || t2 == 15 || t == t2 then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">t == t2</pstext></cu_cause>
          <cu_type constraint="Constraint_UNDEF"/>
          <cu_type constraint="Constraint_NOP"/>
          <cu_type constraint="Constraint_UNKNOWN"/>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="cond__2">&lt;c&gt;</symbol>
      <account encodedin="cond">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="coproc_option">&lt;coproc&gt;</symbol>
      <definition encodedin="cp15">
        <intro>Is the System register encoding space, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">cp15</entry>
                <entry class="symbol">&lt;coproc&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">p14</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">p15</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="opc1__2">&lt;opc1&gt;</symbol>
      <account encodedin="opc1">
        <intro>
          <para>Is the opc1 parameter within the System register encoding space, in the range 0 to 15, encoded in the "opc1" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="Rt__18">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the first general-purpose register that is transferred into, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="Rt2__6">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <intro>
          <para>Is the second general-purpose register that is transferred into, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="CRm">&lt;CRm&gt;</symbol>
      <account encodedin="CRm">
        <intro>
          <para>Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A32.cops_as.sysldst_mov64.movcpgp64.MRRC_A1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if ConditionPassed() then
    EncodingSpecificOperations();
    AArch32_SysRegRead64(cp, ThisInstr(), t, t2);
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
