MVN, MVNS (register-shifted register) Bitwise NOT (register-shifted register) Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. != 1111 0 0 0 1 1 1 1 (0) (0) (0) (0) 0 1 1 MVNS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> 0 MVN{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> let d : integer = UInt(Rd); let m : integer = UInt(Rm); let s : integer = UInt(Rs); let setflags : boolean = (S == '1'); let shift_t : SRType = DecodeRegShift(stype); if d == 15 || m == 15 || s == 15 then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rm> Is the general-purpose source register, encoded in the "Rm" field. <shift> Is the type of shift to be applied to the second source register, stype <shift> 00 LSL 01 LSR 10 ASR 11 ROR <Rs> Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field. if ConditionPassed() then EncodingSpecificOperations(); let shift_n : integer = UInt(R(s)[7:0]); let (shifted, carry) : (bits(32), bit) = Shift_C{32}(R(m), shift_t, shift_n, PSTATE.C); let result : bits(32) = NOT(shifted); R(d) = result; if setflags then PSTATE.N = result[31]; PSTATE.Z = IsZeroBit{32}(result); PSTATE.C = carry; // PSTATE.V unchanged end; end; 2026-03-12 12:23:09 2025-09_rel_asl1