PKHBT, PKHTB Pack Halfword Pack Halfword combines one halfword of its first operand with the other halfword of its shifted second operand. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. This instruction is a data-independent-time instruction as described in About the DIT bit. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 1 1 0 1 0 0 0 0 1 0 PKHBT{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, LSL #<imm>} 1 PKHTB{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, ASR #<imm>} let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let tbform : boolean = (tb == '1'); let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(tb::'0', imm5); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end; 1 1 1 0 1 0 1 0 1 1 0 0 (0) 0 0 PKHBT{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, LSL #<imm>} 1 PKHTB{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, ASR #<imm>} if S == '1' || T == '1' then Undefined(); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let tbform : boolean = (tb == '1'); let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(tb::'0', imm3::imm2); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rn> Is the first general-purpose source register, encoded in the "Rn" field. <Rm> Is the second general-purpose source register, encoded in the "Rm" field. <imm> For the "A1 PKHBT" and "A1 PKHTB" variants: the shift to apply to the value read from <Rm>, encoded in the "imm5" field. For PKHBT, it is one of: omitted No shift, encoded as 0b00000. 1-31 Left shift by specified number of bits, encoded as a binary number. For PKHTB, it is one of: omitted Instruction is a pseudo-instruction and is assembled as though PKHBT{<c>}{<q>} <Rd>, <Rm>, <Rn> had been written. 1-32 Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as 0b00000. Other shift amounts are encoded as binary numbers. An assembler can permit <imm> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly. <imm> For the "T1 PKHBT" and "T1 PKHTB" variants: the shift to apply to the value read from <Rm>, encoded in the "imm3:imm2" field. For PKHBT, it is one of: omitted No shift, encoded as 0b00000. 1-31 Left shift by specified number of bits, encoded as a binary number. For PKHTB, it is one of: omitted Instruction is a pseudo-instruction and is assembled as though PKHBT{<c>}{<q>} <Rd>, <Rm>, <Rn> had been written. 1-32 Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as 0b00000. Other shift amounts are encoded as binary numbers. An assembler can permit <imm> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly. if ConditionPassed() then EncodingSpecificOperations(); let operand2 : bits(32) = Shift{}(R(m), shift_t, shift_n, PSTATE.C); // PSTATE.C ignored R(d)[15:0] = if tbform then operand2[15:0] else R(n)[15:0]; R(d)[31:16] = if tbform then R(n)[31:16] else operand2[31:16]; end; 2026-03-12 12:23:09 2025-09_rel_asl1