PLI (immediate, literal)
Preload Instruction (immediate, literal)
Preload Instruction signals the memory system that instruction
memory accesses from a specified address are likely in the near
future. The memory system can respond by taking actions that are
expected to speed up the memory accesses when they do occur, such
as pre-loading the cache line containing the specified address into
the instruction cache.
The effect of a PLI instruction
is IMPLEMENTATION DEFINED.
For more information, see Preloading caches.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
For the literal forms of the instruction, encoding T3 is used, or Rn is encoded as 0b1111 in encoding A1, to indicate that the PC is the base register.
The alternative literal syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
,
T2
and
T3
)
.
1
1
1
1
0
1
0
0
1
0
1
(1)
(1)
(1)
(1)
PLI{<c>}{<q>} [<Rn> {, #{+/-}<imm>}]
PLI{<c>}{<q>} <label>
PLI{<c>}{<q>} [PC, #{+/-}<imm>]
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let add : boolean = (U == '1');
1
1
1
1
1
0
0
1
1
0
0
1
!= 1111
1
1
1
1
PLI{<c>}{<q>} [<Rn> {, #{+}<imm>}]
if Rn == '1111' then See("encoding T3"); end;
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm12);
let add : boolean = TRUE;
1
1
1
1
1
0
0
1
0
0
0
1
!= 1111
1
1
1
1
1
1
0
0
PLI{<c>}{<q>} [<Rn> {, #-<imm>}]
if Rn == '1111' then See("encoding T3"); end;
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm8);
let add : boolean = FALSE;
1
1
1
1
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
PLI{<c>}{<q>} <label>
PLI{<c>}{<q>} [PC, #{+/-}<imm>]
let n : integer = 15;
let imm32 : bits(32) = ZeroExtend{}(imm12);
let add : boolean = (U == '1');
<c>
For the "A1" variant: see Standard assembler syntax fields. Must be AL or omitted.
<c>
For the "T1", "T2", and "T3" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field.
+/-
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For the "A1" variant: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<imm>
For the "T1" variant: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
<imm>
For the "T2" variant: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.
<imm>
For the "T3" variant: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.
<label>
The label of the instruction that is likely to be accessed in the near future. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. The offset must be in the range –4095 to 4095.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE.
If the offset is negative, imm32 is equal to minus the offset and add == FALSE.
+
Specifies the offset is added to the base register.
if ConditionPassed() then
EncodingSpecificOperations();
let base : bits(32) = if n == 15 then AlignDownSize(PC32(),4) else R(n);
let address : bits(32) = if add then (base + imm32) else (base - imm32);
Hint_PreloadInstr(address);
end;
2026-03-12 12:23:09
2025-09_rel_asl1