RFE, RFEDA, RFEDB, RFEIA, RFEIB
Return From Exception
Return From Exception loads two consecutive memory locations using
an address in a base register:
The word loaded from the lower address is treated as an instruction address. The PE branches to it.
The word loaded from the higher address is used to restore PSTATE. This word must be in the format of an SPSR.
An address adjusted by the size of the data loaded can optionally be
written back to the base register.
The PE checks the value of the word loaded from the higher address
for an illegal return event. See Illegal
return events from AArch32 state.
RFE is UNDEFINED in Hyp mode and
CONSTRAINED UNPREDICTABLE in User mode.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
RFEFA, RFEEA, RFEFD, and RFEED are pseudo-instructions for RFEDA, RFEDB, RFEIA, and RFEIB respectively, referring to their use for popping data from Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
1
1
1
1
1
0
0
0
1
(0)
(0)
(0)
(0)
(1)
(0)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
0
0
RFEDA{<c>}{<q>} <Rn>{!}
RFEFA{<c>}{<q>} <Rn>{!}
1
0
RFEDB{<c>}{<q>} <Rn>{!}
RFEEA{<c>}{<q>} <Rn>{!}
0
1
RFE{IA}{<c>}{<q>} <Rn>{!}
RFEFD{<c>}{<q>} <Rn>{!}
1
1
RFEIB{<c>}{<q>} <Rn>{!}
RFEED{<c>}{<q>} <Rn>{!}
let n : integer = UInt(Rn);
let wback : boolean = (W == '1');
let increment : boolean = (U == '1');
let wordhigher : boolean = (P == U);
if n == 15 then UnpredictableProcedure(); end;
1
1
1
0
1
0
0
0
0
0
1
(1)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
RFEDB{<c>}{<q>} <Rn>{!}
RFEFA{<c>}{<q>} <Rn>{!}
let n : integer = UInt(Rn);
let wback : boolean = (W == '1');
let increment : boolean = FALSE;
let wordhigher : boolean = FALSE;
if n == 15 then UnpredictableProcedure(); end;
if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;
1
1
1
0
1
0
0
1
1
0
1
(1)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
RFE{IA}{<c>}{<q>} <Rn>{!}
RFEFD{<c>}{<q>} <Rn>{!}
let n : integer = UInt(Rn);
let wback : boolean = (W == '1');
let increment : boolean = TRUE;
let wordhigher : boolean = FALSE;
if n == 15 then UnpredictableProcedure(); end;
if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;
<c>
For the "A1 Decrement After", "A1 Decrement Before", "A1 Increment After", and "A1 Increment Before" variants: see Standard assembler syntax fields. <c> must be AL or omitted.
<c>
For the "T1" and "T2" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field.
!
The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.
IA
For the "Increment After" variant: is an optional suffix to indicate the Increment After variant.
IA
For the "T2" variant: is an optional suffix for the Increment After form.
if ConditionPassed() then
EncodingSpecificOperations();
if PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL0 then
UnpredictableProcedure(); // UNDEFINED or NOP
else
var address : bits(32) = if increment then R(n) else R(n)-8;
if wordhigher then address = address+4; end;
let new_pc_value : bits(32) = MemA{32}(address);
let spsr : bits(32) = MemA{32}(address+4);
if wback then R(n) = if increment then R(n)+8 else R(n)-8; end;
AArch32_ExceptionReturn(new_pc_value, spsr);
end;
end;
PSTATE.EL == EL0
2026-03-12 12:23:09
2025-09_rel_asl1