RSB, RSBS (immediate)
Reverse Subtract (immediate)
Reverse Subtract (immediate) subtracts a register value from
an immediate value, and writes the result to the destination register.
If the destination register is not the PC, the RSBS variant of the
instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings
where the PC is permitted as the destination register. ARM
deprecates any use of these encodings. However, when the destination
register is the PC:
The RSB variant of the instruction is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
The RSBS variant of the instruction performs an exception return without the use of the stack. In this case:
The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.
The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
The instruction is UNDEFINED in Hyp mode.
The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
0
1
0
0
1
1
0
RSB{<c>}{<q>} {<Rd>, }<Rn>, #<const>
1
RSBS{<c>}{<q>} {<Rd>, }<Rn>, #<const>
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let setflags : boolean = (S == '1');
let imm32 : bits(32) = A32ExpandImm(imm12);
0
1
0
0
0
0
1
0
0
1
RSB<c>{<q>} {<Rd>, }<Rn>, #0
RSBS{<q>} {<Rd>, }<Rn>, #0
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let setflags : boolean = !InITBlock();
let imm32 : bits(32) = Zeros{}; // immediate = #0
1
1
1
1
0
0
1
1
1
0
0
0
RSB{<c>}{<q>} {<Rd>, }<Rn>, #<const>
RSB<c>.W {<Rd>, }<Rn>, #0
1
RSBS{<c>}{<q>} {<Rd>, }<Rn>, #<const>
RSBS.W {<Rd>, }<Rn>, #0
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let setflags : boolean = (S == '1');
let imm32 : bits(32) = T32ExpandImm(i::imm3::imm8);
// Armv8-A removes UNPREDICTABLE for R13
if d == 15 || n == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rd>
For the "A1 RSB" and "A1 RSBS" variants: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>. Arm deprecates using the PC as the destination register, but if the PC is used:
For the RSB variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
For the RSBS variant, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>.
<Rd>
For the "T1", "T2 RSB", and "T2 RSBS" variants: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>.
<Rn>
For the "A1 RSB" and "A1 RSBS" variants: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.
<Rn>
For the "T1", "T2 RSB", and "T2 RSBS" variants: is the general-purpose source register, encoded in the "Rn" field.
<const>
For the "A1 RSB" and "A1 RSBS" variants: an immediate value. See Modified immediate constants in A32 instructions for the range of values.
<const>
For the "T2 RSB" and "T2 RSBS" variants: an immediate value. See Modified immediate constants in T32 instructions for the range of values.
if ConditionPassed() then
EncodingSpecificOperations();
let (result, nzcv) : (bits(32), bits(4)) = AddWithCarry{32}(NOT(R(n)), imm32, '1');
if d == 15 then // Can only occur for A32 encoding
if setflags then
ALUExceptionReturn(result);
else
ALUWritePC(result);
end;
else
R(d) = result;
if setflags then
PSTATE.[N,Z,C,V] = nzcv;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1