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<instructionsection id="RSC_i" title="RSC, RSCS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A32"/>
  </docvars>
  <heading>RSC, RSCS (immediate)</heading>
  <desc>
    <brief>
      <para>Reverse Subtract with Carry (immediate)</para>
    </brief>
    <authored>
      <para>Reverse Subtract with Carry (immediate) subtracts a register
value and the value of NOT (Carry flag) from an immediate value,
and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the RSCS variant of the
instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings
where the PC is permitted as the destination register. ARM
deprecates any use of these encodings. However, when the destination
register is the PC:</para>
      <list type="unordered">
        <listitem>
          <content>The RSC variant of the instruction is an interworking branch, see <xref linkend="ARMARM_BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content>
        </listitem>
        <listitem>
          <content>The RSCS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered">
              <listitem>
                <content>The PE branches to the address written to the PC, and restores <xref linkend="ARMARM_CHDEDFDC">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content>
              </listitem>
              <listitem>
                <content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="ARMARM_CHDDDJDB">Illegal return events from AArch32 state</xref>.</content>
              </listitem>
              <listitem>
                <content>The instruction is <arm-defined-word>UNDEFINED</arm-defined-word> in Hyp mode.</content>
              </listitem>
              <listitem>
                <content>The instruction is <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> in User mode and System mode.</content>
              </listitem>
            </list>
          </content>
        </listitem>
      </list>
    </authored>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEIIDCEG">About the DIT bit</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A32"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="32" psname="A32.dp.dpimm.intdp2reg_imm.RSC_i_A1" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" width="1" name="S" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"/>
        </box>
      </regdiagram>
      <encoding name="RSC_i_A1" oneofinclass="2" oneof="2" label="RSC" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="RSC"/>
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>RSC{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  {</text><a hover="Is the general-purpose destination register, encoded in the &quot;Rd&quot; field. If omitted, this register is the same as &lt;Rn&gt;. Arm deprecates using the PC as the destination register, but if the PC is used:&#10;&#10;&#10;&#10;  * For the RSC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see x[Pseudocode description of operations on the AArch32 general-purpose registers and the PC](BEICJFEH).&#10;  * For the RSCS variant, the instruction performs an exception return, that restores x[PSTATE](CHDEDFDC) from SPSR_&lt;current_mode&gt;." link="Rd__11">&lt;Rd&gt;</a><text>, }</text><a hover="Is the general-purpose source register, encoded in the &quot;Rn&quot; field. The PC can be used, but this is deprecated." link="Rn__25">&lt;Rn&gt;</a><text>, #</text><a hover="An immediate value. See x[Modified immediate constants in A32 instructions](BABHDAJF) for the range of values." link="const__16">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="RSCS_i_A1" oneofinclass="2" oneof="2" label="RSCS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="RSCS"/>
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>RSCS{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  {</text><a hover="Is the general-purpose destination register, encoded in the &quot;Rd&quot; field. If omitted, this register is the same as &lt;Rn&gt;. Arm deprecates using the PC as the destination register, but if the PC is used:&#10;&#10;&#10;&#10;  * For the RSC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see x[Pseudocode description of operations on the AArch32 general-purpose registers and the PC](BEICJFEH).&#10;  * For the RSCS variant, the instruction performs an exception return, that restores x[PSTATE](CHDEDFDC) from SPSR_&lt;current_mode&gt;." link="Rd__11">&lt;Rd&gt;</a><text>, }</text><a hover="Is the general-purpose source register, encoded in the &quot;Rn&quot; field. The PC can be used, but this is deprecated." link="Rn__25">&lt;Rn&gt;</a><text>, #</text><a hover="An immediate value. See x[Modified immediate constants in A32 instructions](BABHDAJF) for the range of values." link="const__16">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A32.dp.dpimm.intdp2reg_imm.RSC_i_A1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let setflags : boolean = (S == '1');
let imm32 : bits(32) = A32ExpandImm(imm12);</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RSC_i_A1, RSCS_i_A1" symboldefcount="1">
      <symbol link="cond__2">&lt;c&gt;</symbol>
      <account encodedin="cond">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_i_A1, RSCS_i_A1" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_i_A1, RSCS_i_A1" symboldefcount="1">
      <symbol link="Rd__11">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem>
              <content>For the RSC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content>
            </listitem>
            <listitem>
              <content>For the RSCS variant, the instruction performs an exception return, that restores <xref linkend="CHDEDFDC">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_i_A1, RSCS_i_A1" symboldefcount="1">
      <symbol link="Rn__25">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_i_A1, RSCS_i_A1" symboldefcount="1">
      <symbol link="const__16">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>An immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A32.dp.dpimm.intdp2reg_imm.RSC_i_A1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if ConditionPassed() then
    EncodingSpecificOperations();
    let (result, nzcv) : (bits(32), bits(4)) = AddWithCarry{32}(NOT(R(n)), imm32, PSTATE.C);
    if d == 15 then
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
        end;
    else
        R(d) = result;
        if setflags then
            PSTATE.[N,Z,C,V] = nzcv;
        end;
    end;
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
