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<instructionsection id="SDIV_a32" title="SDIV -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="mnemonic" value="SDIV"/>
  </docvars>
  <heading>SDIV</heading>
  <desc>
    <brief>
      <para>Signed Divide</para>
    </brief>
    <authored>
      <para>Signed Divide divides a 32-bit signed integer register value
by a 32-bit signed integer register value, and writes the result
to the destination register. The condition flags are not affected.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> behavior of this instruction, see <xref linkend="ARMARM_CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Overflow</para>
      <para>If the signed integer division <hexnumber>0x80000000</hexnumber> / <hexnumber>0xFFFFFFFF</hexnumber> is performed, the pseudocode produces the intermediate integer result +2<sup>31</sup>, that overflows the 32-bit signed integer range. No indication of this overflow case is produced, and the 32-bit result written to <syntax>&lt;Rd&gt;</syntax> must be the bottom 32 bits of the binary representation of +2<sup>31</sup>. So the result of the division is <hexnumber>0x80000000</hexnumber>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A32"/>
        <docvar key="mnemonic" value="SDIV"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A32.media.smul_div.SDIV_A1" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" psbits="xxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="7" width="3" name="op2" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="SDIV_A1" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="SDIV"/>
        </docvars>
        <asmtemplate><text>SDIV{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  {</text><a hover="Is the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="Rd">&lt;Rd&gt;</a><text>, }</text><a hover="Is the first general-purpose source register holding the dividend, encoded in the &quot;Rn&quot; field." link="Rn__28">&lt;Rn&gt;</a><text>, </text><a hover="Is the second general-purpose source register holding the divisor, encoded in the &quot;Rm&quot; field." link="Rm__17">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A32.media.smul_div.SDIV_A1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let a : integer = UInt(Ra);
if d == 15 || n == 15 || m == 15 || a != 15 then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">Ra != '1111'</pstext></cu_cause>
          <cu_type constraint="Constraint_UNDEF"/>
          <cu_type constraint="Constraint_NOP"/>
          <cu_type constraint="Constraint_NONE"/>
          <cu_type>
            <cu_type_text>The instruction executes as described, and the register specified by Ra becomes UNKNOWN.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="SDIV"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="16x2" psname="T32.w.lmul_div.div.SDIV_T1" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" psbits="xxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="7" width="4" name="op2" usename="1" settings="4" psbits="xxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="SDIV_T1" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="SDIV"/>
        </docvars>
        <asmtemplate><text>SDIV{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}  {</text><a hover="Is the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="Rd">&lt;Rd&gt;</a><text>, }</text><a hover="Is the first general-purpose source register holding the dividend, encoded in the &quot;Rn&quot; field." link="Rn__28">&lt;Rn&gt;</a><text>, </text><a hover="Is the second general-purpose source register holding the divisor, encoded in the &quot;Rm&quot; field." link="Rm__17">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.lmul_div.div.SDIV_T1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let a : integer = UInt(Ra);
// Armv8-A removes UNPREDICTABLE for R13
if d == 15 || n == 15 || m == 15 || a != 15 then UnpredictableProcedure(); end;</pstext></ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">Ra != '1111'</pstext></cu_cause>
          <cu_type constraint="Constraint_UNDEF"/>
          <cu_type constraint="Constraint_NOP"/>
          <cu_type constraint="Constraint_NONE"/>
          <cu_type>
            <cu_type_text>The instruction executes as described, and the register specified by Ra becomes UNKNOWN.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="cond__2">&lt;c&gt;</symbol>
      <account encodedin="cond">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="Rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="Rn__28">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the dividend, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="Rm__17">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the divisor, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A32.media.smul_div.SDIV_A1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if ConditionPassed() then
    EncodingSpecificOperations();
    let dividend : integer = SInt(R(n));
    let divisor : integer  = SInt(R(m));
    var result : integer;
    if divisor == 0 then
        result = 0;
    elsif (dividend &lt; 0) == (divisor &lt; 0) then
        result = Abs(dividend) DIVRM Abs(divisor);    // same signs - positive result
    else
        result = -(Abs(dividend) DIVRM Abs(divisor)); // different signs - negative result
    end;
    R(d) = result[31:0];
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
