SHA1C
SHA1 hash update (choose)
SHA1 hash update (choose).
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
0
0
0
0
1
1
0
0
0
SHA1C.32 <Qd>, <Qn>, <Qm>
if !IsFeatureImplemented(FEAT_SHA1) then Undefined(); end;
if Q != '1' then Undefined(); end;
if Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
1
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
SHA1C.32 <Qd>, <Qn>, <Qm>
if InITBlock() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_SHA1) then Undefined(); end;
if Q != '1' then Undefined(); end;
if Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckCryptoEnabled32();
var x : bits(128) = Q(d>>1);
var y : bits(32) = Q(n>>1)[31:0]; // Note: 32 bits wide
let w : bits(128) = Q(m>>1);
for e = 0 to 3 do
let t : bits(32) = SHAchoose(x[63:32], x[95:64], x[127:96]);
y = y + ROL(x[31:0], 5) + t + w[e*:32];
x[63:32] = ROL(x[63:32], 30);
let yx : bits(160) = ROL(y::x, 32);
(y, x) = (yx[128+:32], yx[0+:128]);
end;
Q(d>>1) = x;
end;
2026-03-12 12:23:09
2025-09_rel_asl1