SHSUB8
Signed Halving Subtract 8
Signed Halving Subtract 8 performs four signed 8-bit integer
subtractions, halves the results, and writes the results to the
destination register.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
0
1
1
0
0
0
1
1
(1)
(1)
(1)
(1)
1
1
1
1
SHSUB8{<c>}{<q>} {<Rd>, }<Rn>, <Rm>
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
1
1
1
1
1
0
1
0
1
1
0
0
1
1
1
1
0
0
1
0
SHSUB8{<c>}{<q>} {<Rd>, }<Rn>, <Rm>
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
// Armv8-A removes UNPREDICTABLE for R13
if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rd>
Is the general-purpose destination register, encoded in the "Rd" field.
<Rn>
Is the first general-purpose source register, encoded in the "Rn" field.
<Rm>
Is the second general-purpose source register, encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
let diff1 : integer = SInt(R(n)[7:0]) - SInt(R(m)[7:0]);
let diff2 : integer = SInt(R(n)[15:8]) - SInt(R(m)[15:8]);
let diff3 : integer = SInt(R(n)[23:16]) - SInt(R(m)[23:16]);
let diff4 : integer = SInt(R(n)[31:24]) - SInt(R(m)[31:24]);
R(d)[7:0] = diff1[8:1];
R(d)[15:8] = diff2[8:1];
R(d)[23:16] = diff3[8:1];
R(d)[31:24] = diff4[8:1];
end;
2026-03-12 12:23:09
2025-09_rel_asl1