SMULWB, SMULWT
Signed Multiply (word by halfword)
Signed
Multiply (word by halfword) multiplies a signed 32-bit quantity
and a signed 16-bit quantity. The signed 16-bit quantity is taken
from either the bottom or the top half of its source register. The
other half of the second source register is ignored. The top 32
bits of the 48-bit product are written to the destination register.
The bottom 16 bits of the 48-bit product are ignored. No overflow
is possible during this instruction.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
0
0
0
1
0
0
1
0
(0)
(0)
(0)
(0)
1
1
0
0
SMULWB{<c>}{<q>} {<Rd>, }<Rn>, <Rm>
1
SMULWT{<c>}{<q>} {<Rd>, }<Rn>, <Rm>
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let m_high : boolean = (M == '1');
if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
SMULWB{<c>}{<q>} {<Rd>, }<Rn>, <Rm>
1
SMULWT{<c>}{<q>} {<Rd>, }<Rn>, <Rm>
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let m_high : boolean = (M == '1');
// Armv8-A removes UNPREDICTABLE for R13
if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rd>
Is the general-purpose destination register, encoded in the "Rd" field.
<Rn>
Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
<Rm>
Is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <y>), encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
let operand2 : bits(16) = if m_high then R(m)[31:16] else R(m)[15:0];
let product : integer = SInt(R(n)) * SInt(operand2);
R(d) = product[47:16];
// Signed overflow cannot occur
end;
2026-03-12 12:23:09
2025-09_rel_asl1