STLEX Store-Release Exclusive Word Store-Release Exclusive Word stores a word from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. Aborts and alignment If a synchronous Data Abort exception is generated by the execution of this instruction: Memory is not updated. <Rd> is not updated. A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules: If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated. Otherwise, it is IMPLEMENTATION DEFINED whether the exception is generated. If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated. This instruction is a data-independent-time instruction as described in About the DIT bit. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 1 0 0 0 (1) (1) 1 0 1 0 0 1 STLEX{<c>}{<q>} <Rd>, <Rt>, [<Rn>] let d : integer = UInt(Rd); let t : integer = UInt(Rt); let n : integer = UInt(Rn); if d == 15 || t == 15 || n == 15 then UnpredictableProcedure(); end; if d == n || d == t then UnpredictableProcedure(); end; d == t d == n The instruction performs the store to an UNKNOWN address. 1 1 1 0 1 0 0 0 1 1 0 0 (1) (1) (1) (1) 1 1 1 0 STLEX{<c>}{<q>} <Rd>, <Rt>, [<Rn>] let d : integer = UInt(Rd); let t : integer = UInt(Rt); let n : integer = UInt(Rn); if d == 15 || t == 15 || n == 15 then UnpredictableProcedure(); end; if d == n || d == t then UnpredictableProcedure(); end; d == t d == n The instruction performs the store to an UNKNOWN address. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is: 0 If the operation updates memory. 1 If the operation fails to update memory. <Rt> Is the general-purpose register to be transferred, encoded in the "Rt" field. <Rn> Is the general-purpose base register, encoded in the "Rn" field. if ConditionPassed() then EncodingSpecificOperations(); let address : bits(32) = R(n); if AArch32_ExclusiveMonitorsPass(address,4) then MemO{32}(address) = R(t); R(d) = ZeroExtend{32}('0'); else R(d) = ZeroExtend{32}('1'); end; end; 2026-03-12 12:23:09 2025-09_rel_asl1