STM (User registers) Store Multiple (User registers) In an EL1 mode other than System mode, Store Multiple (User registers) stores multiple User mode registers to consecutive memory locations using an address from a base register. The PE reads the base register value normally, using the current mode to determine the correct Banked version of the register. This instruction cannot writeback to the base register. Store Multiple (User registers) is UNDEFINED in Hyp mode, and CONSTRAINED UNPREDICTABLE in User or System modes. Armv8.2 permits the deprecation of some Store Multiple ordering behaviors in AArch32 state, for more information see FEAT_LSMAOC. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. This instruction is a data-independent-time instruction as described in About the DIT bit. != 1111 1 0 0 1 (0) 0 STM{<amode>}{<c>}{<q>} <Rn>, <registers>^ let n : integer = UInt(Rn); let registers : bits(16) = register_list; let increment : boolean = (U == '1'); let wordhigher : boolean = (P == U); if n == 15 || BitCount(registers) < 1 then UnpredictableProcedure(); end; BitCount(registers) < 1 The instruction operates as an STM with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. <amode> is one of: DA Decrement After. The consecutive memory addresses end at the address in the base register. Encoded as P = 0, U = 0. ED Empty Descending. For this instruction, a synonym for DA. DB Decrement Before. The consecutive memory addresses end one word below the address in the base register. Encoded as P = 1, U = 0. FD Full Descending. For this instruction, a synonym for DB. IA Increment After. The consecutive memory addresses start at the address in the base register. This is the default. Encoded as P = 0, U = 1. EA Empty Ascending. For this instruction, a synonym for IA. IB Increment Before. The consecutive memory addresses start one word above the address in the base register. Encoded as P = 1, U = 1. FA Full Ascending. For this instruction, a synonym for IB. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rn> Is the general-purpose base register, encoded in the "Rn" field. <registers> Is a list of one or more registers, separated by commas and surrounded by { and }. It specifies the set of registers to be stored by the STM instruction. The registers are stored with the lowest-numbered register to the lowest memory address, through to the highest-numbered register to the highest memory address. See also Encoding of lists of general-purpose registers and the PC. if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then Undefined(); elsif PSTATE.M IN {M32_User,M32_System} then UnpredictableProcedure(); else let length : integer = 4*BitCount(registers); var address : bits(32) = if increment then R(n) else R(n)-length; if wordhigher then address = address+4; end; for i = 0 to 14 do if registers[i] == '1' then // Store User mode register MemS{32}(address) = Rmode(i, M32_User); address = address + 4; end; end; if registers[15] == '1' then MemS{32}(address) = PCStoreValue(); end; end; end; PSTATE.M IN {M32_User,M32_System} The instruction operates as an STM with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. 2026-03-12 12:23:09 2025-09_rel_asl1