STRBT
Store Register Byte Unprivileged
Store Register Byte Unprivileged stores a byte from a register to
memory. For information about memory accesses see
Memory accesses.
The memory access is restricted as if the PE were running in User
mode. This makes no difference if the PE is actually running in User
mode.
STRBT is UNPREDICTABLE in Hyp mode.
The T32 instruction uses an offset addressing mode, that calculates
the address used for the memory access from a base register value
and an immediate offset, and leaves the base register unchanged.
The A32 instruction uses a post-indexed addressing mode, that uses a
base register value as the address for the memory access, and
calculates a new address from a base register value and an offset
and writes it back to the base register. The offset can be an
immediate value or an optionally-shifted register value.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
)
.
!= 1111
0
1
0
0
1
1
0
STRBT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>}
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let postindex : boolean = TRUE;
let add : boolean = (U == '1');
let register_form : boolean = FALSE;
let imm32 : bits(32) = ZeroExtend{}(imm12);
let m : integer = ARBITRARY : integer;
let shift_n : integer = ARBITRARY : integer;
let shift_t : SRType = ARBITRARY : SRType;
if t == 15 || n == 15 || n == t then UnpredictableProcedure(); end;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is UNKNOWN.
n == t
n == 15
The instruction uses post-indexed addressing with the base register as PC. This is handled as described in Using R15.
The instruction is treated as if bit[24] == 1 and bit[21] == 0. The instruction uses immediate offset addressing with the base register as PC, without writeback.
!= 1111
0
1
1
0
1
1
0
0
STRBT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>}
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let postindex : boolean = TRUE;
let add : boolean = (U == '1');
let register_form : boolean = TRUE;
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm5);
let imm32 : bits(32) = ARBITRARY : bits(32);
if t == 15 || n == 15 || n == t || m == 15 then UnpredictableProcedure(); end;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is UNKNOWN.
n == t
n == 15
The instruction uses post-indexed addressing with the base register as PC. This is handled as described in Using R15.
The instruction is treated as if bit[24] == 1 and bit[21] == 0. The instruction uses immediate offset addressing with the base register as PC, without writeback.
1
1
1
1
1
0
0
0
0
0
0
0
!= 1111
1
1
1
0
STRBT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
if Rn == '1111' then Undefined(); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let postindex : boolean = FALSE;
let add : boolean = TRUE;
let register_form : boolean = FALSE;
let imm32 : bits(32) = ZeroExtend{}(imm8);
let m : integer = ARBITRARY : integer;
let shift_n : integer = ARBITRARY : integer;
let shift_t : SRType = ARBITRARY : SRType;
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 then UnpredictableProcedure(); end;
t == 15
The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is UNKNOWN.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rt>
For the "A1" variant: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.
<Rt>
For the "A2" and "T1" variants: is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field.
+/-
For the "A1" variant: specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
+/-
For the "A2" variant: specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
<imm>
For the "A1" variant: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.
<imm>
For the "T1" variant: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.
<Rm>
Is the general-purpose index register, encoded in the "Rm" field.
<shift>
The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts applied to a register.
+
Specifies the offset is added to the base register.
if ConditionPassed() then
EncodingSpecificOperations();
if PSTATE.EL == EL2 then UnpredictableProcedure(); end; // Hyp mode
let offset : bits(32) = (if register_form then Shift{32}(R(m), shift_t, shift_n, PSTATE.C)
else imm32);
let offset_addr : bits(32) = if add then (R(n) + offset) else (R(n) - offset);
let address : bits(32) = if postindex then R(n) else offset_addr;
MemU_unpriv{8}(address) = R(t)[7:0];
if postindex then R(n) = offset_addr; end;
end;
PSTATE.EL == EL2
The instruction executes as STRB (immediate).
2026-03-12 12:23:09
2025-09_rel_asl1