TBB, TBH Table Branch Byte or Halfword Table Branch Byte or Halfword causes a PC-relative forward branch using a table of single byte or halfword offsets. A base register provides a pointer to the table, and a second register supplies an index into the table. The branch length is twice the value returned from the table. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. 1 1 1 0 1 0 0 0 1 1 0 1 (1) (1) (1) (1) (0) (0) (0) (0) 0 0 0 0 TBB{<c>}{<q>} [<Rn>, <Rm>] 1 TBH{<c>}{<q>} [<Rn>, <Rm>, LSL #1] let n : integer = UInt(Rn); let m : integer = UInt(Rm); let is_tbh : boolean = (H == '1'); // Armv8-A removes UNPREDICTABLE for R13 if m == 15 then UnpredictableProcedure(); end; if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rn> Is the general-purpose base register holding the address of the table of branch lengths, encoded in the "Rn" field. The PC can be used. If it is, the table immediately follows this instruction. <Rm> For the "Byte" variant: is the general-purpose index register, encoded in the "Rm" field. This register contains an integer pointing to a single byte in the table. The offset in the table is the value of the index. <Rm> For the "Halfword" variant: is the general-purpose index register, encoded in the "Rm" field. This register contains an integer pointing to a halfword in the table. The offset in the table is twice the value of the index. if ConditionPassed() then EncodingSpecificOperations(); var halfwords : integer; if is_tbh then halfwords = UInt(MemU{16}(R(n)+LSL(R(m), 1))); else halfwords = UInt(MemU{8}(R(n)+R(m))); end; BranchWritePC(PC32() + 2*halfwords, BranchType_INDIR); end; 2026-03-12 12:23:09 2025-09_rel_asl1