TST (register-shifted register) Test (register-shifted register) Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. This instruction is a data-independent-time instruction as described in About the DIT bit. != 1111 0 0 0 1 0 0 0 1 (0) (0) (0) (0) 0 1 TST{<c>}{<q>} <Rn>, <Rm>, <type> <Rs> let n : integer = UInt(Rn); let m : integer = UInt(Rm); let s : integer = UInt(Rs); let shift_t : SRType = DecodeRegShift(stype); if n == 15 || m == 15 || s == 15 then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rn> Is the first general-purpose source register, encoded in the "Rn" field. <Rm> Is the second general-purpose source register, encoded in the "Rm" field. <type> Is the type of shift to be applied to the second source register, stype <type> 00 LSL 01 LSR 10 ASR 11 ROR <Rs> Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field. if ConditionPassed() then EncodingSpecificOperations(); let shift_n : integer = UInt(R(s)[7:0]); let (shifted, carry) : (bits(32), bit) = Shift_C{32}(R(m), shift_t, shift_n, PSTATE.C); let result : bits(32) = R(n) AND shifted; PSTATE.N = result[31]; PSTATE.Z = IsZeroBit{32}(result); PSTATE.C = carry; // PSTATE.V unchanged end; 2026-03-12 12:23:09 2025-09_rel_asl1