UXTH
Unsigned Extend Halfword
Unsigned
Extend Halfword extracts a 16-bit value from a register, zero-extends
it to 32 bits, and writes the result to the destination register.
The instruction can specify a rotation by 0, 8, 16, or 24 bits before
extracting the 16-bit value.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
1
1
0
1
1
1
1
1
1
1
1
(0)
(0)
0
1
1
1
UXTH{<c>}{<q>} {<Rd>, }<Rm> {, ROR #<amount>}
let d : integer = UInt(Rd);
let m : integer = UInt(Rm);
let rotation : integer = UInt(rotate::'000');
if d == 15 || m == 15 then UnpredictableProcedure(); end;
1
0
1
1
0
0
1
0
1
0
UXTH{<c>}{<q>} {<Rd>, }<Rm>
let d : integer = UInt(Rd);
let m : integer = UInt(Rm);
let rotation : integer = 0;
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
(0)
UXTH{<c>}{<q>} {<Rd>, }<Rm> {, ROR #<amount>}
UXTH{<c>}.W {<Rd>, }<Rm>
let d : integer = UInt(Rd);
let m : integer = UInt(Rm);
let rotation : integer = UInt(rotate::'000');
// Armv8-A removes UNPREDICTABLE for R13
if d == 15 || m == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rd>
Is the general-purpose destination register, encoded in the "Rd" field.
<Rm>
Is the general-purpose source register, encoded in the "Rm" field.
<amount>
Is the rotate amount,
rotate
<amount>
00
[absent]
01
8
10
16
11
24
if ConditionPassed() then
EncodingSpecificOperations();
let rotated : bits(32) = ROR(R(m), rotation);
R(d) = ZeroExtend{32}(rotated[15:0]);
end;
2026-03-12 12:23:09
2025-09_rel_asl1