VBIF
Vector Bitwise Insert if False
Vector Bitwise Insert if False inserts each bit from the first
source register into the destination register if the
corresponding bit of the second source register is 0, otherwise
leaves the bit in the destination register unchanged.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
VBIF{<c>}{<q>}{.<dt>} {<Dd>, }<Dn>, <Dm>
1
VBIF{<c>}{<q>}{.<dt>} {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if op == '00' then See("VEOR"); end;
var operation : VBitOps;
if op == '01' then operation = VBitOps_VBSL; end;
if op == '10' then operation = VBitOps_VBIT; end;
if op == '11' then operation = VBitOps_VBIF; end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
0
1
1
0
0
0
1
1
0
VBIF{<c>}{<q>}{.<dt>} {<Dd>, }<Dn>, <Dm>
1
VBIF{<c>}{<q>}{.<dt>} {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if op == '00' then See("VEOR"); end;
var operation : VBitOps;
if op == '01' then operation = VBitOps_VBSL; end;
if op == '10' then operation = VBitOps_VBIT; end;
if op == '11' then operation = VBitOps_VBIF; end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
An optional data type. It is ignored by assemblers, and does not affect the encoding.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
case operation of
when VBitOps_VBIF => D(d+r) = (D(d+r) AND D(m+r)) OR (D(n+r) AND NOT(D(m+r)));
when VBitOps_VBIT => D(d+r) = (D(n+r) AND D(m+r)) OR (D(d+r) AND NOT(D(m+r)));
when VBitOps_VBSL => D(d+r) = (D(n+r) AND D(d+r)) OR (D(m+r) AND NOT(D(d+r)));
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1