VCGE (immediate #0)
Vector Compare Greater Than or Equal to Zero
Vector Compare Greater Than or Equal to Zero takes each element in a
vector, and compares it with zero. If it is greater than or equal to
zero, the corresponding element in the destination vector is set to
all ones. Otherwise, it is set to all zeros.
The operand vector elements are the same type, and are signed integers or
floating-point numbers.
The result vector elements are fields the same size as the
operand vector elements.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
0
1
0
0
0
1
0
0
VCGE{<c>}{<q>}.<dt> {<Dd>, }<Dm>, #0
1
VCGE{<c>}{<q>}.<dt> {<Qd>, }<Qm>, #0
if size == '11' then Undefined(); end;
if F == '1' && size == '00' then Undefined(); end;
if F == '1' && size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let floating_point : boolean = (F == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
1
0
0
VCGE{<c>}{<q>}.<dt> {<Dd>, }<Dm>, #0
1
VCGE{<c>}{<q>}.<dt> {<Qd>, }<Qm>, #0
if size == '11' then Undefined(); end;
if F == '1' && size == '00' then Undefined(); end;
if F == '1' && size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
if F == '1' && size == '01' && InITBlock() then UnpredictableProcedure(); end;
if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end;
let floating_point : boolean = (F == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
F == '1' && size == '01' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the operands,
F
size
<dt>
0
00
S8
0
01
S16
0
10
S32
1
01
F16
1
10
F32
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dm>
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
var test_passed : boolean;
if floating_point then
let zero : bits(esize) = FPZero{}('0');
test_passed = FPCompareGE{esize}(D(m+r)[e*:esize], zero, StandardFPCR());
else
test_passed = (SInt(D(m+r)[e*:esize]) >= 0);
end;
D(d+r)[e*:esize] = if test_passed then Ones{esize} else Zeros{esize};
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1