VCGT (register)
Vector Compare Greater Than
Vector Compare Greater Than takes each element in a vector, and
compares it with the corresponding element of a second vector. If
the first is greater than the second, the corresponding element in
the destination vector is set to all ones. Otherwise, it is set to
all zeros.
The operand vector elements are the same type, and are signed integers,
unsigned integers, or floating-point numbers.
The result vector elements are fields the same size as the
operand vector elements.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
This instruction is a data-independent-time instruction as described in About the DIT bit.
This instruction is used by the alias
VCLT (register)
Never
See
below for details of when the alias is preferred.
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
and
T2
)
.
1
1
1
1
0
0
1
0
0
0
1
1
0
0
VCGT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VCGT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size == '11' then Undefined(); end;
let vtype : VCGTtype = if U == '1' then VCGTtype_unsigned else VCGTtype_signed;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
0
0
1
1
0
1
1
1
1
0
0
0
VCGT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VCGT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let vtype : VCGTtype = VCGTtype_fp;
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
0
0
0
1
1
0
0
VCGT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VCGT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size == '11' then Undefined(); end;
let vtype : VCGTtype = if U == '1' then VCGTtype_unsigned else VCGTtype_signed;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
VCGT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VCGT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
if sz == '1' && InITBlock() then UnpredictableProcedure(); end;
let vtype : VCGTtype = VCGTtype_fp;
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
sz == '1' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
For the "A1 128-bit SIMD vector", "A1 64-bit SIMD vector", "A2 128-bit SIMD vector", and "A2 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector", "T1 64-bit SIMD vector", "T2 128-bit SIMD vector", and "T2 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
For the "A1 128-bit SIMD vector", "A1 64-bit SIMD vector", "T1 128-bit SIMD vector", and "T1 64-bit SIMD vector" variants: is the data type for the elements of the operands,
U
size
<dt>
0
00
S8
0
01
S16
0
10
S32
1
00
U8
1
01
U16
1
10
U32
<dt>
For the "A2 128-bit SIMD vector", "A2 64-bit SIMD vector", "T2 128-bit SIMD vector", and "T2 64-bit SIMD vector" variants: is the data type for the elements of the vectors,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
Alias Conditions
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let op1elt : bits(esize) = D(n+r)[e*:esize];
let op2elt : bits(esize) = D(m+r)[e*:esize];
var test_passed : boolean;
case vtype of
when VCGTtype_signed => test_passed = (SInt(op1elt) > SInt(op2elt));
when VCGTtype_unsigned => test_passed = (UInt(op1elt) > UInt(op2elt));
when VCGTtype_fp => test_passed = FPCompareGT{esize}(op1elt, op2elt,
StandardFPCR());
end;
D(d+r)[e*:esize] = if test_passed then Ones{esize} else Zeros{esize};
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1