VCVTR Convert floating-point to integer Convert floating-point to integer converts a value in a register from floating-point to a 32-bit integer, using the rounding mode specified by the FPSCR and places the result in a second register. VCVT (between floating-point and fixed-point, floating-point) describes conversions between floating-point and 16-bit integers. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support. Related encodings: See Floating-point data-processing for the T32 instruction set, or Floating-point data-processing for the A32 instruction set. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 1 1 1 0 1 1 1 1 1 0 x 1 0 0 1 0 0 0 1 VCVTR{<c>}{<q>}.U32.F16 <Sd>, <Sm> 1 0 1 VCVTR{<c>}{<q>}.S32.F16 <Sd>, <Sm> 0 1 0 VCVTR{<c>}{<q>}.U32.F32 <Sd>, <Sm> 1 1 0 VCVTR{<c>}{<q>}.S32.F32 <Sd>, <Sm> 0 1 1 VCVTR{<c>}{<q>}.U32.F64 <Sd>, <Dm> 1 1 1 VCVTR{<c>}{<q>}.S32.F64 <Sd>, <Dm> if opc2 != '000' && opc2 != '10x' then See("Related encodings"); end; if size == '00' then Undefined(); end; if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end; if size == '01' && cond != '1110' then UnpredictableProcedure(); end; let esize : integer{} = 8 << UInt(size); let d : integer = if size == '11' && opc2[2] == '0' then UInt(D::Vd) else UInt(Vd::D); let m : integer = if size == '11' && opc2[2] == '1' then UInt(M::Vm) else UInt(Vm::M); let to_integer : boolean = (opc2[2] == '1'); let unsigned : boolean = (if to_integer then opc2[0] else op) == '0'; let zero_rounding : boolean = to_integer && op == '1'; size == '01' && cond != '1110' The instruction executes as if it passes the Condition code check. The instruction executes as NOP. This means it behaves as if it fails the Condition code check. 1 1 1 0 1 1 1 0 1 1 1 1 1 0 x 1 0 0 1 0 0 0 1 VCVTR{<c>}{<q>}.U32.F16 <Sd>, <Sm> 1 0 1 VCVTR{<c>}{<q>}.S32.F16 <Sd>, <Sm> 0 1 0 VCVTR{<c>}{<q>}.U32.F32 <Sd>, <Sm> 1 1 0 VCVTR{<c>}{<q>}.S32.F32 <Sd>, <Sm> 0 1 1 VCVTR{<c>}{<q>}.U32.F64 <Sd>, <Dm> 1 1 1 VCVTR{<c>}{<q>}.S32.F64 <Sd>, <Dm> if opc2 != '000' && opc2 != '10x' then See("Related encodings"); end; if size == '00' then Undefined(); end; if size == '01' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end; if size == '01' && InITBlock() then UnpredictableProcedure(); end; let esize : integer{} = 8 << UInt(size); let m : integer = if size == '11' && opc2[2] == '1' then UInt(M::Vm) else UInt(Vm::M); let d : integer = if size == '11' && opc2[2] == '0' then UInt(D::Vd) else UInt(Vd::D); let to_integer : boolean = (opc2[2] == '1'); let unsigned : boolean = (if to_integer then opc2[0] else op) == '0'; let zero_rounding : boolean = to_integer && op == '1'; size == '01' && InITBlock() The instruction executes as if it passes the Condition code check. The instruction executes as NOP. This means it behaves as if it fails the Condition code check. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. <Sm> Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field. <Dm> Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); let fpcr : FPCR_Type = EffectiveFPCR(); let rounding : FPRounding = if zero_rounding then FPRounding_ZERO else FPRoundingMode(fpcr); if to_integer then case esize of when 16 => S(d) = FPToFixed{32, 16}(H(m), 0, unsigned, fpcr, rounding); when 32 => S(d) = FPToFixed{32, 32}(S(m), 0, unsigned, fpcr, rounding); when 64 => S(d) = FPToFixed{32, 64}(D(m), 0, unsigned, fpcr, rounding); end; else case esize of when 16 => H(d) = FixedToFP{16, 32}(S(m), 0, unsigned, fpcr, rounding); when 32 => S(d) = FixedToFP{32, 32}(S(m), 0, unsigned, fpcr, rounding); when 64 => D(d) = FixedToFP{64, 32}(S(m), 0, unsigned, fpcr, rounding); end; end; end; 2026-03-12 12:23:09 2025-09_rel_asl1