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<instructionsection id="VCVTT" title="VCVTT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd"/>
    <docvar key="mnemonic" value="VCVTT"/>
  </docvars>
  <heading>VCVTT</heading>
  <desc>
    <brief>
      <para>Convert to or from a half-precision value in the top half of a single-precision register</para>
    </brief>
    <authored>
      <para>Convert to or from a half-precision value in the top half of a
single-precision register does one of the following:</para>
      <list type="unordered">
        <listitem>
          <content>Converts the half-precision value in the top half of a single-precision register to single-precision and writes the result to a single-precision register.</content>
        </listitem>
        <listitem>
          <content>Converts the half-precision value in the top half of a single-precision register to double-precision and writes the result to a double-precision register.</content>
        </listitem>
        <listitem>
          <content>Converts the single-precision value in a single-precision register to half-precision and writes the result into the top half of a single-precision register, preserving the other half of the destination register.</content>
        </listitem>
        <listitem>
          <content>Converts the double-precision value in a double-precision register to half-precision and writes the result into the top half of a single-precision register, preserving the other half of the destination register.</content>
        </listitem>
      </list>
      <para>Depending on settings in the <xref linkend="ARMARM_AArch32.cpacr">CPACR</xref>,
<xref linkend="ARMARM_AArch32.nsacr">NSACR</xref>,
<xref linkend="ARMARM_AArch32.hcptr">HCPTR</xref>, and
<xref linkend="ARMARM_AArch32.fpexc">FPEXC</xref> registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be <arm-defined-word>UNDEFINED</arm-defined-word>, or
trapped to Hyp mode.
For more information see <xref linkend="ARMARM_CIHIDDFF">Enabling Advanced
SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1"/>
        <docvar key="instr-class" value="fpsimd"/>
        <docvar key="isa" value="A32"/>
        <docvar key="mnemonic" value="VCVTT"/>
      </docvars>
      <iclassintro count="4"/>
      <regdiagram form="32" psname="A32.cops_as.fpdp.fpdp2reg.VCVTT_A1_SH" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="D" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="18" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="16" width="1" name="op" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="7" name="T" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="6" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="1" name="M" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="4" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="VCVTT_A1_SH" oneofinclass="4" oneof="8" label="Half-precision to single-precision" bitdiffs="op == 0 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="A32"/>
          <docvar key="convert-type" value="half-to-single"/>
          <docvar key="mnemonic" value="VCVTT"/>
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTT{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.F32.F16  </text><a hover="Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the &quot;Vd:D&quot; field." link="Vd_D">&lt;Sd&gt;</a><text>, </text><a hover="Is the 32-bit name of the SIMD&amp;FP source register, encoded in the &quot;Vm:M&quot; field." link="Vm_M__2">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_A1_DH" oneofinclass="4" oneof="8" label="Half-precision to double-precision" bitdiffs="op == 0 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="convert-type" value="half-to-double"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="A32"/>
          <docvar key="mnemonic" value="VCVTT"/>
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTT{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.F64.F16  </text><a hover="Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the &quot;D:Vd&quot; field." link="D_Vd">&lt;Dd&gt;</a><text>, </text><a hover="Is the 32-bit name of the SIMD&amp;FP source register, encoded in the &quot;Vm:M&quot; field." link="Vm_M__2">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_A1_HS" oneofinclass="4" oneof="8" label="Single-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="A32"/>
          <docvar key="convert-type" value="single-to-half"/>
          <docvar key="mnemonic" value="VCVTT"/>
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTT{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.F16.F32  </text><a hover="Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the &quot;Vd:D&quot; field." link="Vd_D">&lt;Sd&gt;</a><text>, </text><a hover="Is the 32-bit name of the SIMD&amp;FP source register, encoded in the &quot;Vm:M&quot; field." link="Vm_M__2">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_A1_HD" oneofinclass="4" oneof="8" label="Double-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="A1"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="A32"/>
          <docvar key="convert-type" value="double-to-half"/>
          <docvar key="mnemonic" value="VCVTT"/>
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTT{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.F16.F64  </text><a hover="Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the &quot;Vd:D&quot; field." link="Vd_D">&lt;Sd&gt;</a><text>, </text><a hover="Is the 64-bit name of the SIMD&amp;FP source register, encoded in the &quot;M:Vm&quot; field." link="M_Vm__2">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A32.cops_as.fpdp.fpdp2reg.VCVTT_A1_SH" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let d : integer = if sz == '1' &amp;&amp; op == '0' then UInt(D::Vd) else UInt(Vd::D);
let m : integer = if sz == '1' &amp;&amp; op == '1' then UInt(M::Vm) else UInt(Vm::M);
let uses_double : boolean = (sz == '1');
let convert_from_half : boolean = (op == '0');
let lowbit : integer{} = (if T == '1' then 16 else 0);</pstext></ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1"/>
        <docvar key="instr-class" value="fpsimd"/>
        <docvar key="isa" value="T32"/>
        <docvar key="mnemonic" value="VCVTT"/>
      </docvars>
      <iclassintro count="4"/>
      <regdiagram form="16x2" psname="T32.w.cpaf.fpdp.fp_2r.VCVTT_T1_SH" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="D" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="18" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="16" width="1" name="op" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="7" name="T" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="6" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="1" name="M" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="4" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="VCVTT_T1_SH" oneofinclass="4" oneof="8" label="Half-precision to single-precision" bitdiffs="op == 0 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="T32"/>
          <docvar key="convert-type" value="half-to-single"/>
          <docvar key="mnemonic" value="VCVTT"/>
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTT{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.F32.F16  </text><a hover="Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the &quot;Vd:D&quot; field." link="Vd_D">&lt;Sd&gt;</a><text>, </text><a hover="Is the 32-bit name of the SIMD&amp;FP source register, encoded in the &quot;Vm:M&quot; field." link="Vm_M__2">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_T1_DH" oneofinclass="4" oneof="8" label="Half-precision to double-precision" bitdiffs="op == 0 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="convert-type" value="half-to-double"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="T32"/>
          <docvar key="mnemonic" value="VCVTT"/>
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTT{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.F64.F16  </text><a hover="Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the &quot;D:Vd&quot; field." link="D_Vd">&lt;Dd&gt;</a><text>, </text><a hover="Is the 32-bit name of the SIMD&amp;FP source register, encoded in the &quot;Vm:M&quot; field." link="Vm_M__2">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_T1_HS" oneofinclass="4" oneof="8" label="Single-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="T32"/>
          <docvar key="convert-type" value="single-to-half"/>
          <docvar key="mnemonic" value="VCVTT"/>
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTT{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.F16.F32  </text><a hover="Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the &quot;Vd:D&quot; field." link="Vd_D">&lt;Sd&gt;</a><text>, </text><a hover="Is the 32-bit name of the SIMD&amp;FP source register, encoded in the &quot;Vm:M&quot; field." link="Vm_M__2">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_T1_HD" oneofinclass="4" oneof="8" label="Double-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="T1"/>
          <docvar key="instr-class" value="fpsimd"/>
          <docvar key="isa" value="T32"/>
          <docvar key="convert-type" value="double-to-half"/>
          <docvar key="mnemonic" value="VCVTT"/>
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTT{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="cond__2">&lt;c&gt;</a><text>}{</text><a hover="See x[Standard assembler syntax fields](Babbefhf)." link="qw_option">&lt;q&gt;</a><text>}.F16.F64  </text><a hover="Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the &quot;Vd:D&quot; field." link="Vd_D">&lt;Sd&gt;</a><text>, </text><a hover="Is the 64-bit name of the SIMD&amp;FP source register, encoded in the &quot;M:Vm&quot; field." link="M_Vm__2">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="T32.w.cpaf.fpdp.fp_2r.VCVTT_T1_SH" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let d : integer = if sz == '1' &amp;&amp; op == '0' then UInt(D::Vd) else UInt(Vd::D);
let m : integer = if sz == '1' &amp;&amp; op == '1' then UInt(M::Vm) else UInt(Vm::M);
let uses_double : boolean = (sz == '1');
let convert_from_half : boolean = (op == '0');
let lowbit : integer{} = (if T == '1' then 16 else 0);</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTT_A1_SH, VCVTT_A1_DH, VCVTT_A1_HS, VCVTT_A1_HD, VCVTT_T1_SH, VCVTT_T1_DH, VCVTT_T1_HS, VCVTT_T1_HD" symboldefcount="1">
      <symbol link="cond__2">&lt;c&gt;</symbol>
      <account encodedin="cond">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_SH, VCVTT_A1_DH, VCVTT_A1_HS, VCVTT_A1_HD, VCVTT_T1_SH, VCVTT_T1_DH, VCVTT_T1_HS, VCVTT_T1_HD" symboldefcount="1">
      <symbol link="qw_option">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_SH, VCVTT_A1_HS, VCVTT_A1_HD, VCVTT_T1_SH, VCVTT_T1_HS, VCVTT_T1_HD" symboldefcount="1">
      <symbol link="Vd_D">&lt;Sd&gt;</symbol>
      <account encodedin="(Vd :: D)">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_SH, VCVTT_A1_DH, VCVTT_A1_HS, VCVTT_T1_SH, VCVTT_T1_DH, VCVTT_T1_HS" symboldefcount="1">
      <symbol link="Vm_M__2">&lt;Sm&gt;</symbol>
      <account encodedin="(Vm :: M)">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_DH, VCVTT_T1_DH" symboldefcount="1">
      <symbol link="D_Vd">&lt;Dd&gt;</symbol>
      <account encodedin="(D :: Vd)">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_HD, VCVTT_T1_HD" symboldefcount="1">
      <symbol link="M_Vm__2">&lt;Dm&gt;</symbol>
      <account encodedin="(M :: Vm)">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A32.cops_as.fpdp.fpdp2reg.VCVTT_A1_SH" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if ConditionPassed() then
    EncodingSpecificOperations();
    CheckVFPEnabled(TRUE);
    var hp : bits(16);
    let fpcr : FPCR_Type = EffectiveFPCR();
    if convert_from_half then
        hp = S(m)[lowbit+15:lowbit];
        if uses_double then
            D(d) = FPConvert{64, 16}(hp, fpcr);
        else
            S(d) = FPConvert{32, 16}(hp, fpcr);
        end;
    else
        if uses_double then
            hp = FPConvert{16, 64}(D(m), fpcr);
        else
            hp = FPConvert{16, 32}(S(m), fpcr);
        end;
        S(d)[lowbit+15:lowbit] = hp;
    end;
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
