VDOT (by element)
BFloat16 floating-point indexed dot product (vector, by element)
BFloat16 floating-point indexed dot product (vector, by element).
This instruction delimits the source vectors into pairs of
16-bit BF16 elements. Each pair of elements in the first source
vector is multiplied by the indexed pair of elements in the second
source vector. The resulting single-precision products are then
summed and added destructively to the single-precision element
in the destination vector which aligns with the pair of BFloat16 values
in the first source vector. The instruction does not update the FPSCR exception status.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
0
VDOT{<q>}.BF16 <Dd>, <Dn>, <Dm>[<index>]
1
VDOT{<q>}.BF16 <Qd>, <Qn>, <Dm>[<index>]
if !IsFeatureImplemented(FEAT_AA32BF16) then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1') then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(Vm);
let i : integer = UInt(M);
let regs : integer = if Q == '1' then 2 else 1;
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
0
VDOT{<q>}.BF16 <Dd>, <Dn>, <Dm>[<index>]
1
VDOT{<q>}.BF16 <Qd>, <Qn>, <Dm>[<index>]
if InITBlock() then UnpredictableProcedure(); end;
if !IsFeatureImplemented(FEAT_AA32BF16) then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1') then Undefined(); end;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(Vm);
let i : integer = UInt(M);
let regs : integer = if Q == '1' then 2 else 1;
<q>
See Standard assembler syntax fields.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "Vm" field.
<index>
Is the element index in the range 0 to 1, encoded in the "M" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
CheckAdvSIMDEnabled();
let fpcr : FPCR_Type = StandardFPCR();
var operand1 : bits(64);
var operand2 : bits(64);
var result : bits(64);
operand2 = Din(m);
for r = 0 to regs-1 do
operand1 = Din(n+r);
result = Din(d+r);
for e = 0 to 1 do
let elt1_a : bits(16) = operand1[(2 * e + 0)*:16];
let elt1_b : bits(16) = operand1[(2 * e + 1)*:16];
let elt2_a : bits(16) = operand2[(2 * i + 0)*:16];
let elt2_b : bits(16) = operand2[(2 * i + 1)*:16];
let sum : bits(32) = FPAdd_BF16(BFMulH(elt1_a, elt2_a, fpcr),
BFMulH(elt1_b, elt2_b, fpcr), fpcr);
result[e*:32] = FPAdd_BF16(result[e*:32], sum, fpcr);
end;
D(d+r) = result;
end;
2026-03-12 12:23:09
2025-09_rel_asl1