VDUP (general-purpose register)
Duplicate general-purpose register to vector
Duplicate general-purpose register to vector
duplicates an element from a general-purpose
register into every element of the destination vector.
The destination vector elements can be 8-bit, 16-bit, or 32-bit
fields. The source element is the least significant 8, 16, or 32
bits of the general-purpose register. There is no distinction between
data types.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
1
1
1
0
1
0
1
0
1
1
0
1
(0)
(0)
(0)
(0)
0
VDUP{<c>}{<q>}.<size> <Dd>, <Rt>
1
VDUP{<c>}{<q>}.<size> <Qd>, <Rt>
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let t : integer = UInt(Rt);
let regs : integer = if Q == '0' then 1 else 2;
if B::E == '11' then Undefined(); end;
let esize : integer{} = 32 >> UInt(B::E);
let elements : integer = 64 DIV esize;
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 then UnpredictableProcedure(); end;
1
1
1
0
1
1
1
0
1
0
1
0
1
1
0
1
(0)
(0)
(0)
(0)
0
VDUP{<c>}{<q>}.<size> <Dd>, <Rt>
1
VDUP{<c>}{<q>}.<size> <Qd>, <Rt>
if Q == '1' && Vd[0] == '1' then Undefined(); end;
let d : integer = UInt(D::Vd);
let t : integer = UInt(Rt);
let regs : integer = if Q == '0' then 1 else 2;
if B::E == '11' then Undefined(); end;
let esize : integer{} = 32 >> UInt(B::E);
let elements : integer = 64 DIV esize;
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields. Arm strongly recommends that any VDUP instruction is unconditional, see Conditional execution.
<q>
See Standard assembler syntax fields.
<size>
The data size for the elements of the destination vector. It must be one of:
8
Encoded as [b, e] = 0b10.
16
Encoded as [b, e] = 0b01.
32
Encoded as [b, e] = 0b00.
<Dd>
The destination vector for a doubleword operation.
<Rt>
The Arm source register.
<Qd>
The destination vector for a quadword operation.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let scalar : bits(esize) = R(t)[esize-1:0];
for r = 0 to regs-1 do
for e = 0 to elements-1 do
D(d+r)[e*:esize] = scalar;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1