VFMA
Vector Fused Multiply Accumulate
Vector Fused Multiply Accumulate multiplies corresponding elements
of two vectors, and accumulates the results into the elements of the
destination vector. The instruction does not round the result of the
multiply before the accumulation.
Depending on settings in the CPACR,
NSACR,
HCPTR, and
FPEXC registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
and
T2
)
.
1
1
1
1
0
0
1
0
0
0
1
1
0
0
1
0
VFMA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm>
1
VFMA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let advsimd : boolean = TRUE;
let op1_neg : boolean = (op == '1');
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
!= 1111
1
1
1
0
1
1
0
1
0
0
0
0
1
VFMA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm>
1
0
VFMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>
1
1
VFMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>
if FPSCR().Len != '000' || FPSCR().Stride != '00' then Undefined(); end;
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if size == '01' && cond != '1110' then UnpredictableProcedure(); end;
let advsimd : boolean = FALSE;
let op1_neg : boolean = (op == '1');
let esize : integer{} = 8 << UInt(size);
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let n : integer = if size == '11' then UInt(N::Vn) else UInt(Vn::N);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
let floating_point : boolean = ARBITRARY : boolean;
let regs : integer = ARBITRARY : integer;
let elements : integer = ARBITRARY : integer;
size == '01' && cond != '1110'
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
0
VFMA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm>
1
VFMA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
if sz == '1' && InITBlock() then UnpredictableProcedure(); end;
let advsimd : boolean = TRUE;
let op1_neg : boolean = (op == '1');
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
sz == '1' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
1
1
1
0
1
1
1
0
1
1
0
1
0
0
0
0
1
VFMA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm>
1
0
VFMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>
1
1
VFMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>
if FPSCR().Len != '000' || FPSCR().Stride != '00' then Undefined(); end;
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if size == '01' && InITBlock() then UnpredictableProcedure(); end;
let advsimd : boolean = FALSE;
let op1_neg : boolean = (op == '1');
let esize : integer{} = 8 << UInt(size);
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let n : integer = if size == '11' then UInt(N::Vn) else UInt(Vn::N);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
let floating_point : boolean = ARBITRARY : boolean;
let regs : integer = ARBITRARY : integer;
let elements : integer = ARBITRARY : integer;
size == '01' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "A2 Double-precision scalar", "A2 Half-precision scalar", and "A2 Single-precision scalar" variants: see Standard assembler syntax fields.
<c>
For the "T1 128-bit SIMD vector", "T1 64-bit SIMD vector", "T2 Double-precision scalar", "T2 Half-precision scalar", and "T2 Single-precision scalar" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
<Sn>
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.
<Sm>
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if advsimd then // Advanced SIMD instruction
let fpcr : FPCR_Type = StandardFPCR();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
var op1elt : bits(esize) = D(n+r)[e*:esize];
if op1_neg then op1elt = FPNeg{esize}(op1elt, fpcr); end;
D(d+r)[e*:esize] = FPMulAdd{esize}(D(d+r)[e*:esize],
op1elt, D(m+r)[e*:esize], fpcr);
end;
end;
else // VFP instruction
let fpcr : FPCR_Type = EffectiveFPCR();
case esize of
when 16 =>
let op16 : bits(16) = if op1_neg then FPNeg{16}(H(n), fpcr) else H(n);
H(d) = FPMulAdd{16}(H(d), op16, H(m), fpcr);
when 32 =>
let op32 : bits(32) = if op1_neg then FPNeg{32}(S(n), fpcr) else S(n);
S(d) = FPMulAdd{32}(S(d), op32, S(m), fpcr);
when 64 =>
let op64 : bits(64) = if op1_neg then FPNeg{64}(D(n), fpcr) else D(n);
D(d) = FPMulAdd{64}(D(d), op64, D(m), fpcr);
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1