VLD3 (single 3-element structure to all lanes)
Load single 3-element structure and replicate to all lanes of three registers
Load single 3-element structure and replicate to all lanes of three
registers loads one 3-element structure from memory into all lanes
of three registers. For details of the addressing mode, see
Advanced SIMD addressing mode.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information, see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLD3 (single 3-element structure to all lanes).
For more information about the variants of this instruction, see Advanced SIMD addressing mode.
Alignment
Standard alignment rules apply, see Alignment support.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
1
0
0
1
1
0
1
1
1
0
0
1
1
1
1
VLD3{<c>}{<q>}.<size> <list>, [<Rn>]
1
1
0
1
VLD3{<c>}{<q>}.<size> <list>, [<Rn>]!
N
N
Z
N
VLD3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm>
if size == '11' || a == '1' then Undefined(); end;
let ebytes : integer{} = 1 << UInt(size);
let inc : integer = if T == '0' then 1 else 2;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d3 > 31 then UnpredictableProcedure(); end;
d3 > 31
One or more of the SIMD and floating-point registers are UNKNOWN. If the instruction specifies writeback, the base register becomes UNKNOWN. This behavior does not affect any general-purpose registers.
1
1
1
1
1
0
0
1
1
1
0
1
1
1
0
0
1
1
1
1
VLD3{<c>}{<q>}.<size> <list>, [<Rn>]
1
1
0
1
VLD3{<c>}{<q>}.<size> <list>, [<Rn>]!
N
N
Z
N
VLD3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm>
if size == '11' || a == '1' then Undefined(); end;
let ebytes : integer{} = 1 << UInt(size);
let inc : integer = if T == '0' then 1 else 2;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d3 > 31 then UnpredictableProcedure(); end;
d3 > 31
One or more of the SIMD and floating-point registers are UNKNOWN. If the instruction specifies writeback, the base register becomes UNKNOWN. This behavior does not affect any general-purpose registers.
<c>
For the "A1 Offset" and "A1 Post-indexed" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 Offset" and "T1 Post-indexed" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
Is the data size,
size
<size>
00
8
01
16
10
32
<list>
Is a list containing the 64-bit names of three SIMD&FP registers.
The list must be one of:
{ <Dd>[], <Dd+1>[], <Dd+2>[] }
Single-spaced registers, encoded in the "T" field as 0.
{ <Dd>[], <Dd+2>[], <Dd+4>[] }
Double-spaced registers, encoded in the "T" field as 1.
The register <Dd> is encoded in the "D:Vd" field.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field.
<Rm>
Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let address : bits(32) = R(n);
let esize : integer{} = ebytes * 8;
let element1 : bits(esize) = MemU{8*ebytes}(address);
let element2 : bits(esize) = MemU{8*ebytes}(address+ebytes);
let element3 : bits(esize) = MemU{8*ebytes}(address+2*ebytes);
D(d) = Replicate{64}(element1);
D(d2) = Replicate{64}(element2);
D(d3) = Replicate{64}(element3);
if wback then
if register_index then
R(n) = R(n) + R(m);
else
R(n) = R(n) + 3*ebytes;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1