VLD4 (single 4-element structure to all lanes)
Load single 4-element structure and replicate to all lanes of four registers
Load single 4-element structure and replicate to all lanes of four
registers loads one 4-element structure from memory into all lanes
of four registers. For details of the addressing mode, see
Advanced SIMD addressing mode.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information, see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLD4 (single 4-element structure to all lanes).
For more information about the variants of this instruction, see Advanced SIMD addressing mode.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' && a == '0' then Undefined(); end;
let ebytes : integer{} = if size == '11' then 4 else 1 << UInt(size);
let alignment : integer{} = (if a == '0' && size != '11' then 1
else 4 << (UInt(size[1]) + UInt(size[0])));
let inc : integer = if T == '0' then 1 else 2;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
One or more of the SIMD and floating-point registers are UNKNOWN. If the instruction specifies writeback, the base register becomes UNKNOWN. This behavior does not affect any general-purpose registers.
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]
1
1
0
1
VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!
N
N
Z
N
VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>
if size == '11' && a == '0' then Undefined(); end;
let ebytes : integer{} = if size == '11' then 4 else 1 << UInt(size);
let alignment : integer{} = (if a == '0' && size != '11' then 1
else 4 << (UInt(size[1]) + UInt(size[0])));
let inc : integer = if T == '0' then 1 else 2;
let d : integer = UInt(D::Vd);
let d2 : integer = d + inc;
let d3 : integer = d2 + inc;
let d4 : integer = d3 + inc;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let wback : boolean = (m != 15);
let register_index : boolean = (m != 15 && m != 13);
if n == 15 || d4 > 31 then UnpredictableProcedure(); end;
d4 > 31
One or more of the SIMD and floating-point registers are UNKNOWN. If the instruction specifies writeback, the base register becomes UNKNOWN. This behavior does not affect any general-purpose registers.
<c>
For the "A1 Offset" and "A1 Post-indexed" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 Offset" and "T1 Post-indexed" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
Is the data size,
size
<size>
00
8
01
16
1x
32
<list>
Is a list containing the 64-bit names of four SIMD&FP registers.
The list must be one of:
{ <Dd>[], <Dd+1>[], <Dd+2>[], <Dd+3>[] }
Single-spaced registers, encoded in the "T" field as 0.
{ <Dd>[], <Dd+2>[], <Dd+4>[], <Dd+6>[] }
Double-spaced registers, encoded in the "T" field as 1.
The register <Dd> is encoded in the "D:Vd" field.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field.
<align>
Is the optional alignment.
Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and is encoded in the "a" field as 0.
Whenever <align> is present, the permitted values and encoding depend on <size>:
<size> == 8
<align> is 32, meaning 32-bit alignment, encoded in the "a" field as 1.
<size> == 16
<align> is 64, meaning 64-bit alignment, encoded in the "a" field as 1.
<size> == 32
<align> can be 64 or 128. 64-bit alignment is encoded in the "a:size<0>" field as 0b10, and 128-bit alignment is encoded in the "a:size<0>" field as 0b11.
: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode.
<Rm>
Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let address : bits(32) = R(n);
let nontemporal : boolean = FALSE;
let privileged : boolean = PSTATE.EL != EL0;
let tagchecked : boolean = FALSE;
let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_LOAD, nontemporal,
tagchecked, privileged);
if !IsAlignedSize(address, alignment) then
let fault : FaultRecord = AlignmentFault(accdesc, ZeroExtend{64}(address));
AArch32_Abort(fault);
end;
let esize : integer{} = ebytes * 8;
let element1 : bits(esize) = MemU{8*ebytes}(address);
let element2 : bits(esize) = MemU{8*ebytes}(address+ebytes);
let element3 : bits(esize) = MemU{8*ebytes}(address+2*ebytes);
let element4 : bits(esize) = MemU{8*ebytes}(address+3*ebytes);
D(d) = Replicate{64}(element1);
D(d2) = Replicate{64}(element2);
D(d3) = Replicate{64}(element3);
D(d4) = Replicate{64}(element4);
if wback then
if register_index then
R(n) = R(n) + R(m);
else
R(n) = R(n) + 4*ebytes;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1