VLDM, VLDMDB, VLDMIA
Load Multiple SIMD&FP registers
Load Multiple SIMD&FP registers loads multiple registers from
consecutive locations in the Advanced SIMD and floating-point
register file using an address from a general-purpose register.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information, see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLDM.
Related encodings: See Advanced SIMD and floating-point 64-bit move for the T32 instruction set, or Advanced SIMD and floating-point 64-bit move for the A32 instruction set.
This instruction is a data-independent-time instruction as described in About the DIT bit.
This instruction is used by the alias
VPOP
P == '0' && U == '1' && W == '1' && Rn == '1101'
See
below for details of when the alias is preferred.
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
and
T2
)
.
!= 1111
1
1
0
1
1
0
1
1
x
x
x
x
x
x
x
0
1
0
1
VLDMDB{<c>}{<q>}{.<size>} <Rn>!, <dreglist>
0
1
VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>
VLDMIA{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>
if P == '0' && U == '0' && W == '0' then See("Related encodings"); end;
if P == '1' && W == '0' then See("VLDR"); end;
if P == U && W == '1' then Undefined(); end;
// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
let single_regs : boolean = FALSE;
let add : boolean = (U == '1');
let wback : boolean = (W == '1');
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm8::'00');
let regs : integer = UInt(imm8) DIVRM 2; // If UInt(imm8) is odd, see "FLDM*X".
if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end;
if regs == 0 || regs > 16 || (d+regs) > 32 then UnpredictableProcedure(); end;
if imm8[0] == '1' && (d+regs) > 16 then UnpredictableProcedure(); end;
regs == 0
The instruction operates as a VLDM with the same addressing mode but loads no registers.
regs > 16 || (d+regs) > 32
One or more of the SIMD and floating-point registers are UNKNOWN. If the instruction specifies writeback, the base register becomes UNKNOWN. This behavior does not affect any general-purpose registers.
!= 1111
1
1
0
1
1
0
1
0
1
0
1
VLDMDB{<c>}{<q>}{.<size>} <Rn>!, <sreglist>
0
1
VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>
VLDMIA{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>
if P == '0' && U == '0' && W == '0' then See("Related encodings"); end;
if P == '1' && W == '0' then See("VLDR"); end;
if P == U && W == '1' then Undefined(); end;
// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
let single_regs : boolean = TRUE;
let add : boolean = (U == '1');
let wback : boolean = (W == '1');
let d : integer = UInt(Vd::D);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm8::'00');
let regs : integer = UInt(imm8);
if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end;
if regs == 0 || (d+regs) > 32 then UnpredictableProcedure(); end;
regs == 0
The instruction operates as a VLDM with the same addressing mode but loads no registers.
(d+regs) > 32
One or more of the SIMD and floating-point registers are UNKNOWN. If the instruction specifies writeback, the base register becomes UNKNOWN. This behavior does not affect any general-purpose registers.
1
1
1
0
1
1
0
1
1
0
1
1
x
x
x
x
x
x
x
0
1
0
1
VLDMDB{<c>}{<q>}{.<size>} <Rn>!, <dreglist>
0
1
VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>
VLDMIA{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>
if P == '0' && U == '0' && W == '0' then See("Related encodings"); end;
if P == '1' && W == '0' then See("VLDR"); end;
if P == U && W == '1' then Undefined(); end;
// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
let single_regs : boolean = FALSE;
let add : boolean = (U == '1');
let wback : boolean = (W == '1');
let d : integer = UInt(D::Vd);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm8::'00');
let regs : integer = UInt(imm8) DIVRM 2; // If UInt(imm8) is odd, see "FLDM*X".
if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end;
if regs == 0 || regs > 16 || (d+regs) > 32 then UnpredictableProcedure(); end;
if imm8[0] == '1' && (d+regs) > 16 then UnpredictableProcedure(); end;
regs == 0
The instruction operates as a VLDM with the same addressing mode but loads no registers.
regs > 16 || (d+regs) > 32
One or more of the SIMD and floating-point registers are UNKNOWN. If the instruction specifies writeback, the base register becomes UNKNOWN. This behavior does not affect any general-purpose registers.
1
1
1
0
1
1
0
1
1
0
1
0
1
0
1
VLDMDB{<c>}{<q>}{.<size>} <Rn>!, <sreglist>
0
1
VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>
VLDMIA{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>
if P == '0' && U == '0' && W == '0' then See("Related encodings"); end;
if P == '1' && W == '0' then See("VLDR"); end;
if P == U && W == '1' then Undefined(); end;
// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
let single_regs : boolean = TRUE;
let add : boolean = (U == '1');
let wback : boolean = (W == '1');
let d : integer = UInt(Vd::D);
let n : integer = UInt(Rn);
let imm32 : bits(32) = ZeroExtend{}(imm8::'00');
let regs : integer = UInt(imm8);
if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UnpredictableProcedure(); end;
if regs == 0 || (d+regs) > 32 then UnpredictableProcedure(); end;
regs == 0
The instruction operates as a VLDM with the same addressing mode but loads no registers.
(d+regs) > 32
One or more of the SIMD and floating-point registers are UNKNOWN. If the instruction specifies writeback, the base register becomes UNKNOWN. This behavior does not affect any general-purpose registers.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred.
<Rn>
Is the general-purpose base register, encoded in the "Rn" field. If writeback is not specified, the PC can be used.
<dreglist>
Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The list must contain at least one register, and must not contain more than 16 registers.
!
Specifies base register writeback,
W
!
0
[absent]
1
[present]
<sreglist>
Is the list of consecutively numbered 32-bit SIMD&FP registers to be transferred. The first register in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must contain at least one register.
Alias Conditions
if ConditionPassed() then
EncodingSpecificOperations();
CheckVFPEnabled(TRUE);
var address : bits(32) = if add then R(n) else R(n)-imm32;
for r = 0 to regs-1 do
if single_regs then
S(d+r) = MemA{32}(address);
address = address+4;
else
let word1 : bits(32) = MemA{32}(address);
let word2 : bits(32) = MemA{32}(address+4);
address = address+8;
// Combine the word-aligned words in the correct order for current endianness.
D(d+r) = if BigEndian(AccessType_ASIMD) then word1::word2 else word2::word1;
end;
end;
if wback then R(n) = if add then R(n)+imm32 else R(n)-imm32; end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1