VMAXNM
Floating-point Maximum Number
This instruction determines the floating-point maximum number.
It handles NaNs in consistence with the IEEE754-2008 specification.
It returns the numerical operand when one operand is numerical
and the other is a quiet NaN, but otherwise the result is identical
to floating-point VMAX.
This instruction is not conditional.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
and
T2
)
.
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
VMAXNM{<q>}.<dt> <Dd>, <Dn>, <Dm>
1
VMAXNM{<q>}.<dt> <Qd>, <Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let maximum : boolean = (op == '0');
let advsimd : boolean = TRUE;
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
VMAXNM{<q>}.F16 <Sd>, <Sn>, <Sm>
1
0
VMAXNM{<q>}.F32 <Sd>, <Sn>, <Sm>
1
1
VMAXNM{<q>}.F64 <Dd>, <Dn>, <Dm>
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
let advsimd : boolean = FALSE;
let maximum : boolean = (op == '0');
let esize : integer{} = 8 << UInt(size);
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let n : integer = if size == '11' then UInt(N::Vn) else UInt(Vn::N);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
let regs : integer = ARBITRARY : integer;
let elements : integer = ARBITRARY : integer;
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
VMAXNM{<q>}.<dt> <Dd>, <Dn>, <Dm>
1
VMAXNM{<q>}.<dt> <Qd>, <Qn>, <Qm>
if InITBlock() then UnpredictableProcedure(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let maximum : boolean = (op == '0');
let advsimd : boolean = TRUE;
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
VMAXNM{<q>}.F16 <Sd>, <Sn>, <Sm>
1
0
VMAXNM{<q>}.F32 <Sd>, <Sn>, <Sm>
1
1
VMAXNM{<q>}.F64 <Dd>, <Dn>, <Dm>
if InITBlock() then UnpredictableProcedure(); end;
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
let advsimd : boolean = FALSE;
let maximum : boolean = (op == '0');
let esize : integer{} = 8 << UInt(size);
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let n : integer = if size == '11' then UInt(N::Vn) else UInt(Vn::N);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
let regs : integer = ARBITRARY : integer;
let elements : integer = ARBITRARY : integer;
InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
<Sn>
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.
<Sm>
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.
EncodingSpecificOperations();
CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if advsimd then // Advanced SIMD instruction
let fpcr : FPCR_Type = StandardFPCR();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let operand1 : bits(esize) = D(n+r)[e*:esize];
let operand2 : bits(esize) = D(m+r)[e*:esize];
if maximum then
D(d+r)[e*:esize] = FPMaxNum{esize}(operand1, operand2, fpcr);
else
D(d+r)[e*:esize] = FPMinNum{esize}(operand1, operand2, fpcr);
end;
end;
end;
else // VFP instruction
let fpcr : FPCR_Type = EffectiveFPCR();
case esize of
when 16 =>
if maximum then
H(d) = FPMaxNum{16}(H(n), H(m), fpcr);
else
H(d) = FPMinNum{16}(H(n), H(m), fpcr);
end;
when 32 =>
if maximum then
S(d) = FPMaxNum{32}(S(n), S(m), fpcr);
else
S(d) = FPMinNum{32}(S(n), S(m), fpcr);
end;
when 64 =>
if maximum then
D(d) = FPMaxNum{64}(D(n), D(m), fpcr);
else
D(d) = FPMinNum{64}(D(n), D(m), fpcr);
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1