VMLAL (by scalar)
Vector Multiply Accumulate Long (by scalar)
Vector Multiply Accumulate Long multiplies elements of a vector by a
scalar, and adds the products to corresponding elements of the
destination vector. The destination vector elements are twice as
long as the elements that are multiplied.
For more information about scalars see
Advanced SIMD scalars.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD data-processing for the T32 instruction set, or Advanced SIMD data-processing for the A32 instruction set.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
!= 11
0
0
1
0
1
0
VMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm[x]>
if size == '11' then See("Related encodings"); end;
if size == '00' || Vd[0] == '1' then Undefined(); end;
let unsigned : boolean = (U == '1');
let add : boolean = (op == '0');
let floating_point : boolean = FALSE;
let long_destination : boolean = TRUE;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let regs : integer = 1;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let m : integer = if size == '01' then UInt(Vm[2:0]) else UInt(Vm);
let index : integer = if size == '01' then UInt(M::Vm[3]) else UInt(M);
1
1
1
1
1
1
1
1
!= 11
0
0
1
0
1
0
VMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm[x]>
if size == '11' then See("Related encodings"); end;
if size == '00' || Vd[0] == '1' then Undefined(); end;
let unsigned : boolean = (U == '1');
let add : boolean = (op == '0');
let floating_point : boolean = FALSE;
let long_destination : boolean = TRUE;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let regs : integer = 1;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let m : integer = if size == '01' then UInt(Vm[2:0]) else UInt(Vm);
let index : integer = if size == '01' then UInt(M::Vm[3]) else UInt(M);
<c>
For the "A1" variant: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1" variant: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the scalar and the elements of the operand vector,
U
size
<dt>
0
01
S16
0
10
S32
1
01
U16
1
10
U32
<Qd>
Is the 128-bit name of the SIMD&FP register holding the accumulate vector, encoded in the "D:Vd" field as <Qd>*2.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm[x]>
Is the 64-bit name of the second SIMD&FP source register holding the scalar. If <dt> is S16 or U16, Dm is restricted to D0-D7. Dm is encoded in "Vm<2:0>", and x is encoded in "M:Vm<3>". If <dt> is S32 or U32, Dm is restricted to D0-D15. Dm is encoded in "Vm", and x is encoded in "M".
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
let fpcr : FPCR_Type = StandardFPCR();
let op2elt : bits(esize) = Din(m)[index*:esize];
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let op1elt : bits(esize) = Din(n+r)[e*:esize];
if floating_point then
let fp_addend : bits(esize) = (if add then FPMul{esize}(op1elt, op2elt, fpcr)
else FPNeg{esize}(FPMul{esize}(op1elt, op2elt,
fpcr),
fpcr));
D(d+r)[e*:esize] = FPAdd{esize}(Din(d+r)[e*:esize], fp_addend, fpcr);
else
let element1 : integer = if unsigned then UInt(op1elt) else SInt(op1elt);
let element2 : integer = if unsigned then UInt(op2elt) else SInt(op2elt);
let addend : integer = if add then element1*element2 else -element1*element2;
if long_destination then
Q(d>>1)[e*:(2*esize)] = Qin(d>>1)[e*:(2*esize)] + addend;
else
D(d+r)[e*:esize] = Din(d+r)[e*:esize] + addend;
end;
end;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1