VMLSL (integer)
Vector Multiply Subtract Long (integer)
Vector Multiply Subtract Long multiplies corresponding elements in two
vectors, and subtract the products from the corresponding elements
of the destination vector. The destination vector element is twice
as long as the elements that are multiplied.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD data-processing for the T32 instruction set, or Advanced SIMD data-processing for the A32 instruction set.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
!= 11
1
0
1
0
0
0
VMLSL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>
if size == '11' then See("Related encodings"); end;
if Vd[0] == '1' then Undefined(); end;
let add : boolean = (op == '0');
let long_destination : boolean = TRUE;
let unsigned : boolean = (U == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = 1;
1
1
1
1
1
1
1
1
!= 11
1
0
1
0
0
0
VMLSL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>
if size == '11' then See("Related encodings"); end;
if Vd[0] == '1' then Undefined(); end;
let add : boolean = (op == '0');
let long_destination : boolean = TRUE;
let unsigned : boolean = (U == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = 1;
<c>
For the "A1" variant: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1" variant: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the operands,
U
size
<dt>
0
00
S8
0
01
S16
0
10
S32
1
00
U8
1
01
U16
1
10
U32
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let op1elt : bits(esize) = Din(n+r)[e*:esize];
let op2elt : bits(esize) = Din(m+r)[e*:esize];
let element1 : integer = if unsigned then UInt(op1elt) else SInt(op1elt);
let element2 : integer = if unsigned then UInt(op2elt) else SInt(op2elt);
let product : integer = element1 * element2;
let addend : integer = if add then product else -product;
if long_destination then
Q(d>>1)[e*:(2*esize)] = Qin(d>>1)[e*:(2*esize)] + addend;
else
D(d+r)[e*:esize] = Din(d+r)[e*:esize] + addend;
end;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1