VMOV (general-purpose register to scalar)
Copy a general-purpose register to a vector element
Copy a general-purpose register to a vector element copies a byte,
halfword, or word from a general-purpose register into an Advanced
SIMD scalar.
On a Floating-point-only system, this instruction transfers
one word to the upper or lower half of a double-precision floating-point
register from a general-purpose register. This is an identical operation
to the Advanced SIMD single word transfer.
For more information about scalars see Advanced SIMD scalars.
Depending on settings in the CPACR,
NSACR,
HCPTR, and
FPEXC registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
1
1
1
0
0
0
1
0
1
1
1
(0)
(0)
(0)
(0)
VMOV{<c>}{<q>}{.<size>} <Dd[x]>, <Rt>
let opc : bits(4) = opc1::opc2;
if opc == '0x10' then Undefined(); end;
let lsb : integer{} = LowestSetBit(opc[0,3]);
let esize : integer{} = 8 << lsb;
let index : integer = UInt(opc[2:lsb]);
let advsimd : boolean = (esize < 32);
let d : integer = UInt(D::Vd);
let t : integer = UInt(Rt);
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 then UnpredictableProcedure(); end;
1
1
1
0
1
1
1
0
0
0
1
0
1
1
1
(0)
(0)
(0)
(0)
VMOV{<c>}{<q>}{.<size>} <Dd[x]>, <Rt>
let opc : bits(4) = opc1::opc2;
if opc == '0x10' then Undefined(); end;
let lsb : integer{} = LowestSetBit(opc[0,3]);
let esize : integer{} = 8 << lsb;
let index : integer = UInt(opc[2:lsb]);
let advsimd : boolean = (esize < 32);
let d : integer = UInt(D::Vd);
let t : integer = UInt(Rt);
// Armv8-A removes UNPREDICTABLE for R13
if t == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<size>
The data size. It must be one of:
8
Encoded as opc1<1> = 1. [x] is encoded in opc1<0>, opc2.
16
Encoded as opc1<1> = 0, opc2<0> = 1. [x] is encoded in opc1<0>, opc2<1>.
32
Encoded as opc1<1> = 0, opc2 = 0b00. [x] is encoded in opc1<0>.
omitted
Equivalent to 32.
<Dd[x]>
The scalar. The register <Dd> is encoded in D:Vd. For details of how [x] is encoded, see the description of <size>.
<Rt>
The source general-purpose register.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
D(d)[index*:esize] = R(t)[esize-1:0];
end;
2026-03-12 12:23:09
2025-09_rel_asl1