VMOV (between two general-purpose registers and two single-precision registers) Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers transfers the contents of two consecutively numbered single-precision Floating-point registers to two general-purpose registers, or the contents of two general-purpose registers to a pair of single-precision Floating-point registers. The general-purpose registers do not have to be contiguous. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VMOV (between two general-purpose registers and two single-precision registers). This instruction is a data-independent-time instruction as described in About the DIT bit. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 VMOV{<c>}{<q>} <Sm>, <Sm1>, <Rt>, <Rt2> 1 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Sm>, <Sm1> let t : integer = UInt(Rt); let t2 : integer = UInt(Rt2); let m : integer = UInt(Vm::M); let m2 : integer = m + 1; let to_arm_registers : boolean = (op == '1'); if t == 15 || t2 == 15 || m == 31 then UnpredictableProcedure(); end; if to_arm_registers && t == t2 then UnpredictableProcedure(); end; to_arm_registers && t == t2 m == 31 One or more of the single-precision registers become UNKNOWN for a move to the single-precision register. The general-purpose registers listed in the instruction become UNKNOWN for a move from the single-precision registers. This behavior does not affect any other general-purpose registers. 1 1 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 VMOV{<c>}{<q>} <Sm>, <Sm1>, <Rt>, <Rt2> 1 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Sm>, <Sm1> let t : integer = UInt(Rt); let t2 : integer = UInt(Rt2); let m : integer = UInt(Vm::M); let m2 : integer = m + 1; let to_arm_registers : boolean = (op == '1'); if t == 15 || t2 == 15 || m == 31 then UnpredictableProcedure(); end; if to_arm_registers && t == t2 then UnpredictableProcedure(); end; to_arm_registers && t == t2 m == 31 One or more of the single-precision registers become UNKNOWN for a move to the single-precision register. The general-purpose registers listed in the instruction become UNKNOWN for a move from the single-precision registers. This behavior does not affect any other general-purpose registers. <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Sm> Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Vm:M" field. <Sm1> Is the 32-bit name of the second SIMD&FP register to be transferred. This is the next SIMD&FP register after <Sm>. <Rt> Is the first general-purpose register that <Sm> will be transferred to or from, encoded in the "Rt" field. <Rt2> Is the second general-purpose register that <Sm1> will be transferred to or from, encoded in the "Rt2" field. if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); if to_arm_registers then R(t) = S(m); R(t2) = S(m2); else S(m) = R(t); S(m2) = R(t2); end; end; 2026-03-12 12:23:09 2025-09_rel_asl1