VNMLA
Vector Negate Multiply Accumulate
Vector Negate Multiply Accumulate multiplies together two
floating-point register values, adds the negation of the
floating-point value in the destination register to the negation of
the product, and writes the result back to the destination register.
Arm recommends that software does not use the VNMLA instruction
in the Round towards Plus Infinity and Round towards Minus Infinity
rounding modes, because the rounding of the product and of the sum
can change the result of the instruction in opposite directions,
defeating the purpose of these rounding modes.
Depending on settings in the CPACR,
NSACR,
HCPTR, and
FPEXC registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
!= 1111
1
1
1
0
0
0
1
1
0
1
0
0
1
VNMLA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm>
1
0
VNMLA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>
1
1
VNMLA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>
if FPSCR().Len != '000' || FPSCR().Stride != '00' then Undefined(); end;
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if size == '01' && cond != '1110' then UnpredictableProcedure(); end;
let vtype : VFPNegMul = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
let esize : integer{} = 8 << UInt(size);
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let n : integer = if size == '11' then UInt(N::Vn) else UInt(Vn::N);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
size == '01' && cond != '1110'
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
1
1
1
0
1
1
1
0
0
0
1
1
0
1
0
0
1
VNMLA{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm>
1
0
VNMLA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>
1
1
VNMLA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>
if FPSCR().Len != '000' || FPSCR().Stride != '00' then Undefined(); end;
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end;
if size == '01' && InITBlock() then UnpredictableProcedure(); end;
let vtype : VFPNegMul = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
let esize : integer{} = 8 << UInt(size);
let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D);
let n : integer = if size == '11' then UInt(N::Vn) else UInt(Vn::N);
let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M);
size == '01' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Sd>
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
<Sn>
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.
<Sm>
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckVFPEnabled(TRUE);
let fpcr : FPCR_Type = EffectiveFPCR();
case esize of
when 16 =>
let product16 : bits(16) = FPMul{}(H(n), H(m), fpcr);
case vtype of
when VFPNegMul_VNMLA => H(d) = FPAdd{16}(FPNeg{16}(H(d), fpcr),
FPNeg{16}(product16, fpcr), fpcr);
when VFPNegMul_VNMLS => H(d) = FPAdd{16}(FPNeg{16}(H(d), fpcr), product16, fpcr);
when VFPNegMul_VNMUL => H(d) = FPNeg{16}(product16, fpcr);
end;
when 32 =>
let product32 : bits(32) = FPMul{}(S(n), S(m), fpcr);
case vtype of
when VFPNegMul_VNMLA => S(d) = FPAdd{32}(FPNeg{32}(S(d), fpcr),
FPNeg{32}(product32, fpcr), fpcr);
when VFPNegMul_VNMLS => S(d) = FPAdd{32}(FPNeg{32}(S(d), fpcr), product32, fpcr);
when VFPNegMul_VNMUL => S(d) = FPNeg{32}(product32, fpcr);
end;
when 64 =>
let product64 : bits(64) = FPMul{}(D(n), D(m), fpcr);
case vtype of
when VFPNegMul_VNMLA => D(d) = FPAdd{64}(FPNeg{64}(D(d), fpcr),
FPNeg{64}(product64, fpcr), fpcr);
when VFPNegMul_VNMLS => D(d) = FPAdd{64}(FPNeg{64}(D(d), fpcr), product64, fpcr);
when VFPNegMul_VNMUL => D(d) = FPNeg{64}(product64, fpcr);
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1