VPMAX (floating-point)
Vector Pairwise Maximum (floating-point)
Vector Pairwise Maximum compares adjacent pairs of elements in two
doubleword vectors, and copies the larger of each pair into the
corresponding element in the destination doubleword vector.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
VPMAX{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
let maximum : boolean = (op == '0');
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
VPMAX{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then Undefined(); end;
if sz == '1' && InITBlock() then UnpredictableProcedure(); end;
let maximum : boolean = (op == '0');
let esize : integer{} = 32 >> UInt(sz);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
sz == '1' && InITBlock()
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
<c>
For the "A1" variant: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1" variant: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
var dest : bits(64);
let fpcr : FPCR_Type = StandardFPCR();
let h : integer = elements DIV 2;
for e = 0 to h-1 do
var op1elt : bits(esize) = D(n)[(2*e)*:esize];
var op2elt : bits(esize) = D(n)[(2*e+1)*:esize];
dest[e*:esize] = (if maximum then FPMax{esize}(op1elt, op2elt, fpcr)
else FPMin{esize}(op1elt, op2elt, fpcr));
op1elt = D(m)[(2*e)*:esize];
op2elt = D(m)[(2*e+1)*:esize];
dest[(e+h)*:esize] = (if maximum then FPMax{esize}(op1elt, op2elt, fpcr)
else FPMin{esize}(op1elt, op2elt, fpcr));
end;
D(d) = dest;
end;
2026-03-12 12:23:09
2025-09_rel_asl1