VQDMULH
Vector Saturating Doubling Multiply Returning High Half
Vector Saturating Doubling Multiply Returning High Half multiplies
corresponding elements in two vectors, doubles the results, and
places the most significant half of the final results in the
destination vector. The results are truncated, for rounded results
see VQRDMULH.
The second operand can be a scalar instead of a vector. For more
information about scalars see Advanced SIMD
scalars.
If any of the results overflow, they are saturated. The cumulative
saturation bit, FPSCR.QC, is set if
saturation occurs. For details see Pseudocode
details of saturation.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
Related encodings: See Advanced SIMD data-processing for the T32 instruction set, or Advanced SIMD data-processing for the A32 instruction set.
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
and
T2
)
.
1
1
1
1
0
0
1
0
0
1
0
1
1
0
0
VQDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VQDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size == '00' || size == '11' then Undefined(); end;
let scalar_form : boolean = FALSE;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
let index : integer = ARBITRARY : integer;
1
1
1
1
0
0
1
1
!= 11
1
1
0
0
1
0
0
VQDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm[x]>
1
VQDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Dm[x]>
if size == '11' then See("Related encodings"); end;
if size == '00' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1') then Undefined(); end;
let scalar_form : boolean = TRUE;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = if size == '01' then UInt(Vm[2:0]) else UInt(Vm);
let index : integer = if size == '01' then UInt(M::Vm[3]) else UInt(M);
let regs : integer = if Q == '0' then 1 else 2;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
1
1
1
0
1
1
1
1
0
1
0
1
1
0
0
VQDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VQDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
if size == '00' || size == '11' then Undefined(); end;
let scalar_form : boolean = FALSE;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
let index : integer = ARBITRARY : integer;
1
1
1
1
1
1
1
1
!= 11
1
1
0
0
1
0
0
VQDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm[x]>
1
VQDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Dm[x]>
if size == '11' then See("Related encodings"); end;
if size == '00' then Undefined(); end;
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1') then Undefined(); end;
let scalar_form : boolean = TRUE;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = if size == '01' then UInt(Vm[2:0]) else UInt(Vm);
let index : integer = if size == '01' then UInt(M::Vm[3]) else UInt(M);
let regs : integer = if Q == '0' then 1 else 2;
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
<c>
For the "A1 128-bit SIMD vector", "A1 64-bit SIMD vector", "A2 128-bit SIMD vector", and "A2 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector", "T1 64-bit SIMD vector", "T2 128-bit SIMD vector", and "T2 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the operands,
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
<Dm[x]>
Is the 64-bit name of the second SIMD&FP source register holding the scalar. If <dt> is S16, Dm is restricted to D0-D7. Dm is encoded in "Vm<2:0>", and x is encoded in "M:Vm<3>". If <dt> is S32, Dm is restricted to D0-D15. Dm is encoded in "Vm", and x is encoded in "M".
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
var op2 : integer;
if scalar_form then op2 = SInt(D(m)[index*:esize]); end;
for r = 0 to regs-1 do
for e = 0 to elements-1 do
if !scalar_form then op2 = SInt(D(m+r)[e*:esize]); end;
let op1 : integer = SInt(D(n+r)[e*:esize]);
// The following only saturates if both op1 and op2 equal -(2^(esize-1))
let (result, sat) : (bits(esize), boolean) = SignedSatQ{esize}((2*op1*op2) >> esize);
D(d+r)[e*:esize] = result;
if sat then FPSCR().QC = '1'; end;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1