VQMOVN, VQMOVUN
Vector Saturating Move and Narrow
Vector Saturating Move and Narrow copies each element of the
operand vector to the corresponding element of the destination vector.
The operand is a quadword vector. The elements can be any
one of:
16-bit, 32-bit, or 64-bit signed integers.
16-bit, 32-bit, or 64-bit unsigned integers.
The result is a doubleword vector. The elements are half the
length of the operand vector elements. If the operand is unsigned,
the results are unsigned. If the operand is signed, the results
can be signed or unsigned.
If any of the results overflow, they are saturated. The cumulative
saturation bit, FPSCR.QC, is set if
saturation occurs. For details see Pseudocode
details of saturation.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
This instruction is used by the aliases
VQRSHRN (zero)
Never
VQRSHRUN (zero)
Never
VQSHRN (zero)
Never
VQSHRUN (zero)
Never
See
below for details of when each alias is preferred.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
0
0
1
x
VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>
0
1
VQMOVUN{<c>}{<q>}.<dt> <Dd>, <Qm>
if op == '00' then See("VMOVN"); end;
if size == '11' || Vm[0] == '1' then Undefined(); end;
let src_unsigned : boolean = (op == '11');
let dest_unsigned : boolean = (op[0] == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
1
x
VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>
0
1
VQMOVUN{<c>}{<q>}.<dt> <Dd>, <Qm>
if op == '00' then See("VMOVN"); end;
if size == '11' || Vm[0] == '1' then Undefined(); end;
let src_unsigned : boolean = (op == '11');
let dest_unsigned : boolean = (op[0] == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let m : integer = UInt(M::Vm);
<c>
For the "A1 Signed result" and "A1 Unsigned result" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 Signed result" and "T1 Unsigned result" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
For the "A1 Signed result" and "T1 Signed result" variants: is the data type for the elements of the operand,
op
size
<dt>
10
00
S16
10
01
S32
10
10
S64
1x
11
RESERVED
11
00
U16
11
01
U32
11
10
U64
<dt>
For the "A1 Unsigned result" and "T1 Unsigned result" variants: is the data type for the elements of the operand,
size
<dt>
00
S16
01
S32
10
S64
11
RESERVED
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Qm>
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
Alias Conditions
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for e = 0 to elements-1 do
let opelt : bits(2*esize) = Qin(m>>1)[e*:(2*esize)];
let element : integer = if src_unsigned then UInt(opelt) else SInt(opelt);
let (res, sat) : (bits(esize), boolean) = SatQ{esize}(element, dest_unsigned);
D(d)[e*:esize] = res;
if sat then FPSCR().QC = '1'; end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1