VQSUB
Vector Saturating Subtract
Vector Saturating Subtract subtracts the elements of the second
operand vector from the corresponding elements of the first operand
vector, and places the results in the destination vector. Signed
and unsigned operations are distinct.
The operand and result elements must all be the same type,
and can be any one of:
8-bit, 16-bit, 32-bit, or 64-bit signed integers.
8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.
If any of the results overflow, they are saturated. The cumulative
saturation bit, FPSCR.QC, is set if
saturation occurs. For details see Pseudocode
details of saturation.
Depending on settings in the CPACR,
NSACR, and
HCPTR registers, and the Security
state and PE mode in which the instruction is executed, an attempt to
execute the instruction might be UNDEFINED, or
trapped to Hyp mode.
For more information see Enabling Advanced
SIMD and floating-point support.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
1
1
1
1
0
0
1
0
0
0
1
0
1
0
VQSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VQSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
let unsigned : boolean = (U == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
1
1
1
1
1
1
1
0
0
0
1
0
1
0
VQSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
1
VQSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end;
let unsigned : boolean = (U == '1');
let esize : integer{} = 8 << UInt(size);
let elements : integer = 64 DIV esize;
let d : integer = UInt(D::Vd);
let n : integer = UInt(N::Vn);
let m : integer = UInt(M::Vm);
let regs : integer = if Q == '0' then 1 else 2;
<c>
For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.
<c>
For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<dt>
Is the data type for the elements of the vectors,
U
size
<dt>
0
00
S8
0
01
S16
0
10
S32
0
11
S64
1
00
U8
1
01
U16
1
10
U32
1
11
U64
<Dd>
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Dn>
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
<Dm>
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
<Qd>
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Qn>
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.
<Qm>
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.
if ConditionPassed() then
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1 do
for e = 0 to elements-1 do
let op1elt : bits(esize) = D(n+r)[e*:esize];
let op2elt : bits(esize) = D(m+r)[e*:esize];
let element1 : integer = if unsigned then UInt(op1elt) else SInt(op1elt);
let element2 : integer = if unsigned then UInt(op2elt) else SInt(op2elt);
let diff : integer = element1 - element2;
let (res, sat) : (bits(esize), boolean) = SatQ{esize}(diff, unsigned);
D(d+r)[e*:esize] = res;
if sat then FPSCR().QC = '1'; end;
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1